summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/agesa/Kconfig2
-rw-r--r--src/cpu/amd/agesa/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family14/Kconfig6
-rw-r--r--src/cpu/amd/agesa/family14/Makefile.inc9
-rw-r--r--src/cpu/amd/agesa/family14/acpi/cpu.asl18
-rw-r--r--src/cpu/amd/agesa/family14/chip_name.c7
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c131
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c99
8 files changed, 0 insertions, 273 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index e4f15960e1..b224fc35a1 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -2,7 +2,6 @@
config CPU_AMD_AGESA
bool
- default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB
default n
@@ -47,6 +46,5 @@ config ENABLE_MRC_CACHE
endif # CPU_AMD_AGESA
-source "src/cpu/amd/agesa/family14/Kconfig"
source "src/cpu/amd/agesa/family15tn/Kconfig"
source "src/cpu/amd/agesa/family16kb/Kconfig"
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index ac16e00eb7..31c2635de3 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
deleted file mode 100644
index fc1b878e63..0000000000
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config CPU_AMD_AGESA_FAMILY14
- bool
- select NO_SMM
- select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
deleted file mode 100644
index 003aa1f532..0000000000
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += fixme.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_14_init.c
-
-subdirs-y += ../../mtrr
diff --git a/src/cpu/amd/agesa/family14/acpi/cpu.asl b/src/cpu/amd/agesa/family14/acpi/cpu.asl
deleted file mode 100644
index 224b227df0..0000000000
--- a/src/cpu/amd/agesa/family14/acpi/cpu.asl
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Processor Object
- *
- */
-Scope (\_SB) { /* define processor scope */
-
- Device (C000) {
- Name (_HID, "ACPI0007")
- Name (_UID, 0)
- }
-
- Device (C001) {
- Name (_HID, "ACPI0007")
- Name (_UID, 1)
- }
-} /* End _SB scope */
diff --git a/src/cpu/amd/agesa/family14/chip_name.c b/src/cpu/amd/agesa/family14/chip_name.c
deleted file mode 100644
index dc0c9df7a5..0000000000
--- a/src/cpu/amd/agesa/family14/chip_name.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_family14_ops = {
- CHIP_NAME("AMD CPU Family 14h Model 00h-0Fh")
-};
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
deleted file mode 100644
index 1da55a77f8..0000000000
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/hpet.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
- PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
- * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
- * set to non-posted regions.
- */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
- PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
- PciData |= 1 << 7; // set NP (non-posted) bit
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
- PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Map the remaining PCI hole as posted MMIO */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
- PciData = 0x00FECF00; // last address before non-posted range
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
- PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Send all IO (0000-FFFF) to southbridge. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
- PciData = 0x0000F000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
- PciData = 0x00000003;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
-
-void amd_initenv(void)
-{
- AMD_INTERFACE_PARAMS AmdParamStruct;
- PCI_ADDR PciAddress;
- UINT32 PciValue;
-
- /* Initialize Subordinate Bus Number and Secondary Bus Number
- * In platform BIOS this address is allocated by PCI enumeration code
- Modify D1F0x18
- */
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = 1;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x18;
- /* Write to D1F0x18 */
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x00010100;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize GMM Base Address for Legacy Bridge Mode
- * Modify B1D5F0x18
- */
- PciAddress.Address.Bus = 1;
- PciAddress.Address.Device = 5;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x18;
-
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x96000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize FB Base Address for Legacy Bridge Mode
- * Modify B1D5F0x10
- */
- PciAddress.Address.Register = 0x10;
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x80000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize GMM Base Address for PCIe Mode
- * Modify B0D1F0x18
- */
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = 1;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x18;
-
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x96000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize FB Base Address for PCIe Mode
- * Modify B0D1F0x10
- */
- PciAddress.Address.Register = 0x10;
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x80000000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize MMIO Base and Limit Address
- * Modify B0D1F0x20
- */
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = 1;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = 0x20;
-
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x96009600;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
- /* Initialize MMIO Prefetchable Memory Limit and Base
- * Modify B0D1F0x24
- */
- PciAddress.Address.Register = 0x24;
- LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
- PciValue |= 0x8FF18001;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-}
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
deleted file mode 100644
index 1d2c294961..0000000000
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <amdblocks/cpu.h>
-#include <amdblocks/smm.h>
-#include <console/console.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <device/device.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-static void model_14_init(struct device *dev)
-{
- msr_t msr;
- int msrno;
-#if CONFIG(LOGICAL_CPUS)
- u32 siblings;
-#endif
- printk(BIOS_DEBUG, "Model 14 Init.\n");
-
- disable_cache();
- /*
- * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
- * by coreboot.
- */
-
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- /* Set shadow WB, RdMEM, WrMEM */
- msr.lo = msr.hi = 0;
- wrmsr(MTRR_FIX_16K_A0000, msr);
- msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(MTRR_FIX_64K_00000, msr);
- wrmsr(MTRR_FIX_16K_80000, msr);
- for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
- wrmsr(msrno, msr);
-
- msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- if (acpi_is_wakeup_s3())
- restore_mtrr();
-
- x86_mtrr_check();
- enable_cache();
-
- /* zero the machine check error status registers */
- mca_clear_status();
-
-#if CONFIG(LOGICAL_CPUS)
- siblings = get_cpu_count() - 1; // minus BSP
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
- /* Write protect SMM space with SMMLOCK. */
- lock_smm();
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = model_14_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */
- { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */
- { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */
- { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */
- { 0, 0 },
-};
-
-static const struct cpu_driver model_14 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 06:27:58 +0000