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-rw-r--r--src/cpu/intel/fsp_model_206ax/Kconfig5
-rw-r--r--src/cpu/intel/haswell/Kconfig5
-rw-r--r--src/cpu/intel/hyperthreading/intel_sibling.c2
-rw-r--r--src/cpu/intel/model_2065x/Kconfig5
-rw-r--r--src/cpu/intel/model_206ax/Kconfig5
-rw-r--r--src/cpu/x86/Kconfig4
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c34
7 files changed, 22 insertions, 38 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 1db5030013..0fb4437cbd 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -37,16 +37,13 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_LAPIC
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
+ select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/fsp_model_206ax/bootblock.c"
-config SERIAL_CPU_INIT
- bool
- default n
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 60c2066b7e..fa02cba2eb 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -22,16 +22,13 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select PARALLEL_CPU_INIT
select PARALLEL_MP
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/haswell/bootblock.c"
-config SERIAL_CPU_INIT
- bool
- default n
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index f30ea45da5..d67a5b829f 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -7,7 +7,7 @@
#include <smp/spinlock.h>
#include <assert.h>
-#if !CONFIG_SERIAL_CPU_INIT
+#if CONFIG_PARALLEL_CPU_INIT
#error Intel hyper-threading requires serialized cpu init
#endif
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index f59845e5d2..3ef314d711 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_CONSTANT_RATE
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
+ select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
@@ -22,10 +23,6 @@ config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_2065x/bootblock.c"
-config SERIAL_CPU_INIT
- bool
- default n
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index eb45bf8e44..a679e00139 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_LAPIC
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
+ select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
@@ -23,10 +24,6 @@ config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"
-config SERIAL_CPU_INIT
- bool
- default n
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 5c37861214..7689d59ae0 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -1,6 +1,6 @@
-config SERIAL_CPU_INIT
+config PARALLEL_CPU_INIT
bool
- default y
+ default n
config UDELAY_IO
bool
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 2aef2a4bcd..09b6b9eeb0 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -406,9 +406,9 @@ void stop_this_cpu(void)
void asmlinkage secondary_cpu_init(unsigned int index)
{
atomic_inc(&active_cpus);
-#if CONFIG_SERIAL_CPU_INIT
- spin_lock(&start_cpu_lock);
-#endif
+
+ if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ spin_lock(&start_cpu_lock);
#ifdef __SSE3__
/*
@@ -421,9 +421,9 @@ void asmlinkage secondary_cpu_init(unsigned int index)
write_cr4(cr4_val);
#endif
cpu_initialize(index);
-#if CONFIG_SERIAL_CPU_INIT
- spin_unlock(&start_cpu_lock);
-#endif
+
+ if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ spin_unlock(&start_cpu_lock);
atomic_dec(&active_cpus);
@@ -439,11 +439,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
- #if !CONFIG_SERIAL_CPU_INIT
- if(cpu==bsp_cpu) {
+
+ if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu==bsp_cpu))
continue;
- }
- #endif
if (!cpu->enabled) {
continue;
@@ -458,9 +456,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
-#if CONFIG_SERIAL_CPU_INIT
- udelay(10);
-#endif
+
+ if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ udelay(10);
}
}
@@ -538,19 +536,17 @@ void initialize_cpus(struct bus *cpu_bus)
#endif
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
- #if !CONFIG_SERIAL_CPU_INIT
/* start all aps at first, so we can init ECC all together */
- start_other_cpus(cpu_bus, info->cpu);
- #endif
+ if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ start_other_cpus(cpu_bus, info->cpu);
#endif
/* Initialize the bootstrap processor */
cpu_initialize(0);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
- #if CONFIG_SERIAL_CPU_INIT
- start_other_cpus(cpu_bus, info->cpu);
- #endif
+ if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);