diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/geode_lx/cpureginit.c | 20 | ||||
| -rw-r--r-- | src/cpu/via/c7/c7_init.c | 2 |
3 files changed, 12 insertions, 12 deletions
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 61874a907a..8bc5cd3320 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -17,7 +17,7 @@ #define PRINTK_IN_CAR 1 #if PRINTK_IN_CAR -#define print_car_debug(x) print_debug(x) +#define print_car_debug(x) printk(BIOS_DEBUG, x) #else #define print_car_debug(x) #endif diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c index 282fa7ed84..9c0a8d9795 100644 --- a/src/cpu/amd/geode_lx/cpureginit.c +++ b/src/cpu/amd/geode_lx/cpureginit.c @@ -170,7 +170,7 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) /* Castle 2.0 BTM periodic sync period. */ /* [40:37] 1 sync record per 256 bytes */ - print_debug("Castle 2.0 BTM periodic sync period.\n"); + printk(BIOS_DEBUG, "Castle 2.0 BTM periodic sync period.\n"); msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); msr.hi |= (0x8 << 5); @@ -180,7 +180,7 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) * LX performance setting. * Enable Quack for fewer re-RAS on the MC */ - print_debug("Enable Quack for fewer re-RAS on the MC\n"); + printk(BIOS_DEBUG, "Enable Quack for fewer re-RAS on the MC\n"); msrnum = GLIU0_ARB; msr = rdmsr(msrnum); msr.hi &= ~ARB_UPPER_DACK_EN_SET; @@ -196,25 +196,25 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) /* GLIU port active enable, limit south pole masters * (AES and PCI) to one outstanding transaction. */ - print_debug(" GLIU port active enable\n"); + printk(BIOS_DEBUG, " GLIU port active enable\n"); msrnum = GLIU1_PORT_ACTIVE; msr = rdmsr(msrnum); msr.lo &= ~0x880; wrmsr(msrnum, msr); /* Set the Delay Control in GLCP */ - print_debug("Set the Delay Control in GLCP\n"); + printk(BIOS_DEBUG, "Set the Delay Control in GLCP\n"); SetDelayControl(dimm0, dimm1, terminated); /* Enable RSDC */ - print_debug("Enable RSDC\n"); + printk(BIOS_DEBUG, "Enable RSDC\n"); msrnum = CPU_AC_SMM_CTL; msr = rdmsr(msrnum); msr.lo |= SMM_INST_EN_SET; wrmsr(msrnum, msr); /* FPU imprecise exceptions bit */ - print_debug("FPU imprecise exceptions bit\n"); + printk(BIOS_DEBUG, "FPU imprecise exceptions bit\n"); msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); msr.lo |= FPU_IE_SET; @@ -222,14 +222,14 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) /* Power Savers (Do after BIST) */ /* Enable Suspend on HLT & PAUSE instructions */ - print_debug("Enable Suspend on HLT & PAUSE instructions\n"); + printk(BIOS_DEBUG, "Enable Suspend on HLT & PAUSE instructions\n"); msrnum = CPU_XC_CONFIG; msr = rdmsr(msrnum); msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; wrmsr(msrnum, msr); /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ - print_debug("Enable SUSP and allow TSC to run in Suspend\n"); + printk(BIOS_DEBUG, "Enable SUSP and allow TSC to run in Suspend\n"); msrnum = CPU_BC_CONF_0; msr = rdmsr(msrnum); msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; @@ -247,10 +247,10 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) } /* Setup throttling delays to proper mode if it is ever enabled. */ - print_debug("Setup throttling delays to proper mode\n"); + printk(BIOS_DEBUG, "Setup throttling delays to proper mode\n"); msrnum = GLCP_TH_OD; msr.hi = 0; msr.lo = 0x00000603C; wrmsr(msrnum, msr); - print_debug("Done cpuRegInit\n"); + printk(BIOS_DEBUG, "Done cpuRegInit\n"); } diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 7f22e59067..054a8744a6 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -122,7 +122,7 @@ static void set_c7_speed(int model) { } break; default: - print_info("CPU type not known, multiplier unchanged.\n"); + printk(BIOS_INFO, "CPU type not known, multiplier unchanged.\n"); } msr.lo = new; |