4 files changed, 36 insertions, 1 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 4ed5d1e5f8..534b1578c9 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -24,6 +24,11 @@
 #include <cpu/x86/msr.h>
 #include "model_206ax.h"
 
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
 static void msr_set_bit(unsigned reg, unsigned bit)
 {
 	msr_t msr = rdmsr(reg);
@@ -43,6 +48,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 
 void intel_model_206ax_finalize_smm(void)
 {
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -67,6 +73,9 @@ void intel_model_206ax_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index 1731322d83..b87e8c2b3e 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -24,6 +24,11 @@
 #include <cpu/x86/msr.h>
 #include "haswell.h"
 
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
 #if 0
 static void msr_set_bit(unsigned reg, unsigned bit)
 {
@@ -46,6 +51,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 void intel_cpu_haswell_finalize_smm(void)
 {
 #if 0
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -70,7 +76,10 @@ void intel_cpu_haswell_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 #endif
 }
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index b37a84cfe7..1835dce3db 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -25,6 +25,11 @@
 #include <cpu/intel/speedstep.h>
 #include "model_2065x.h"
 
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
 static void msr_set_bit(unsigned reg, unsigned bit)
 {
 	msr_t msr = rdmsr(reg);
@@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 
 void intel_model_2065x_finalize_smm(void)
 {
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -67,7 +73,9 @@ void intel_model_2065x_finalize_smm(void)
 	msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
-
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 2c215a4daf..0c1fe75ba7 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -25,6 +25,11 @@
 #include <cpu/intel/speedstep.h>
 #include "model_206ax.h"
 
+/* MSR Documentation based on
+ * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
+ * Document Number 504790
+ * Revision 1.6.0, June 2012 */
+
 static void msr_set_bit(unsigned reg, unsigned bit)
 {
 	msr_t msr = rdmsr(reg);
@@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit)
 
 void intel_model_206ax_finalize_smm(void)
 {
+	/* Lock C-State MSR */
 	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
@@ -68,6 +74,9 @@ void intel_model_206ax_finalize_smm(void)
 	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif
 
+	/* Lock TM interupts - route thermal events to all processors */
 	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+
+	/* Lock memory configuration to protect SMM */
 	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
 }