diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 9 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/socket_940/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/socket_S1G1/Kconfig | 4 |
7 files changed, 4 insertions, 29 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 1ed721f7e0..986c68afc4 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -15,10 +15,6 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x0 - # FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better # yet be dropped completely. config MAX_PHYSICAL_CPUS diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 18a19fc030..686025fda3 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -25,9 +25,6 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) -/* Leave some space for global variable to pass to RAM stage. */ -#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE - /* For CAR with Fam10h. */ #define CacheSizeAPStack 0x400 /* 1K */ @@ -348,7 +345,7 @@ fam10_end_part1: rep stosl /* Set up the stack pointer. */ - movl $(CacheBase + CacheSize - GlobalVarSize), %eax + movl $(CacheBase + CacheSize), %eax movl %eax, %esp post_code(0xa3) @@ -358,7 +355,7 @@ CAR_FAM10_ap: /* * Need to set stack pointer for AP. * It will be from: - * CacheBase + (CacheSize - GlobalVarSize) / 2 + * CacheBase + CacheSize / 2 * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack * So need to get the NodeID and CoreID at first. * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need @@ -392,7 +389,7 @@ roll_cfg: /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp + movl $(CacheBase + CacheSize / 2), %esp subl %eax, %esp /* Retrive init detected. */ diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2aa4f302d3..861948ff57 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -164,12 +164,6 @@ static void post_cache_as_ram(void) set_sysinfo_in_ram(1); // So other core0 could start to train mem -#if CONFIG_MEM_TRAIN_SEQ == 1 -// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - // wait for ap memory to trained -// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c -#endif /*copy and execute coreboot_ram */ copy_and_run(0); /* We will not return */ diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index c5bdb4a5f8..23192f1a06 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -19,10 +19,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - config UDELAY_IO bool default n diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index e34e6f7e20..4ad28a74a6 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -32,7 +32,7 @@ void cpus_ready_for_init(void) { #if CONFIG_MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index 1dbf6526b7..2704876b8f 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -21,8 +21,4 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - endif # CPU_AMD_SOCKET_940 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 284c1812c9..b5090b908e 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -31,8 +31,4 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - endif |