diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/car/disable_cache_as_ram.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/geode_lx/msrinit.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/x86/pae/pgtbl.c | 2 |
7 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 24533c7eb9..7776ae7224 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) #if CONFIG_DCACHE_RAM_SIZE > 0x8000 wrmsr(MTRRfix4K_C0000_MSR, msr); #endif - /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + /* disable fixed mtrr from now on, it will be enabled by ramstage again*/ msr = rdmsr(SYSCFG_MSR); msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index f74f915ec5..97127855be 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -153,7 +153,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) set_sysinfo_in_ram(1); // So other core0 could start to train mem - /*copy and execute coreboot_ram */ + /*copy and execute ramstage */ copy_and_run(); /* We will not return */ diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c index 11182501c1..84fa548d59 100644 --- a/src/cpu/amd/geode_lx/msrinit.c +++ b/src/cpu/amd/geode_lx/msrinit.c @@ -42,11 +42,11 @@ static const msrinit_t msr_table[] = /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. * It doesn't really matter in fact how much, however, because the only usage - * of this extended memory will be to host the coreboot_ram stage at RAMBASE, + * of this extended memory will be to host the ramstage stage at RAMBASE, * currently 1Mb. * These registers will be set to their correct value by the Northbridge init code. * - * WARNING: if coreboot_ram could not be loaded, these registers are probably + * WARNING: if ramstage could not be loaded, these registers are probably * incorrectly set here. You may comment the following two lines and set RAMBASE * to 0x4000 to revert to the previous behavior for LX-boards. */ diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc index a269fb9691..cc350601e2 100644 --- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc @@ -162,7 +162,7 @@ _clear_mtrrs_: post_code(0x38) /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. + * and ramstage. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index b791881d69..e46a2ee3f3 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -227,7 +227,7 @@ before_romstage: post_code(0x38) /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. + * and ramstage. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 887d92bbe6..1a197071c4 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -239,7 +239,7 @@ before_romstage: post_code(0x38) /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. + * and ramstage. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814c5f161f..935473828c 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -1,5 +1,5 @@ /* - 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + 2005.12 yhlu add ramstage cross the vga font buffer handling */ #include <console/console.h> |