diff options
Diffstat (limited to 'src/cpu/x86/mtrr')
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 22 | ||||
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 42 |
2 files changed, 46 insertions, 18 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index aea8e258d4..1c00bd7dcc 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -47,10 +47,29 @@ static void set_var_mtrr( basem.hi = 0; wrmsr(MTRRphysBase_MSR(reg), basem); maskm.lo = ~(size - 1) | 0x800; - maskm.hi = 0x0f; + maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; wrmsr(MTRRphysMask_MSR(reg), maskm); } +static void set_var_mtrr_x( + unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type) + +{ + /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + msr_t basem, maskm; + basem.lo = (base_lo & 0xfffff000) | type; + basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1); + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.hi = (1<<(CPU_ADDR_BITS-32))-1; + if(size_lo) { + maskm.lo = ~(size_lo - 1) | 0x800; + } else { + maskm.lo = 0x800; + maskm.hi &= ~(size_hi - 1); + } + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + static void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ @@ -70,7 +89,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) */ msr_t msr; const unsigned long *msr_addr; - unsigned long cr0; /* Inialize all of the relevant msrs to 0 */ msr.lo = 0; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 1226713cf5..101d11d5e2 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -70,6 +70,25 @@ static void set_var_mtrr( msr_t base, mask; unsigned address_mask_high; + if (reg >= 8) + return; + + // it is recommended that we disable and enable cache when we + // do this. + if (sizek == 0) { + disable_cache(); + + msr_t zero; + zero.lo = zero.hi = 0; + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR(reg), zero); + + enable_cache(); + return; + } + + address_mask_high = ((1u << (address_bits - 32u)) - 1u); base.hi = basek >> 22; @@ -86,25 +105,16 @@ static void set_var_mtrr( mask.lo = 0; } - if (reg >= 8) - return; - // it is recommended that we disable and enable cache when we // do this. disable_cache(); - if (sizek == 0) { - msr_t zero; - zero.lo = zero.hi = 0; - /* The invalid bit is kept in the mask, so we simply clear the - relevant mask register to disable a range. */ - wrmsr (MTRRphysMask_MSR(reg), zero); - } else { - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - base.lo |= type; - mask.lo |= 0x800; - wrmsr (MTRRphysBase_MSR(reg), base); - wrmsr (MTRRphysMask_MSR(reg), mask); - } + + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + base.lo |= type; + mask.lo |= 0x800; + wrmsr (MTRRphysBase_MSR(reg), base); + wrmsr (MTRRphysMask_MSR(reg), mask); + enable_cache(); } |