summaryrefslogtreecommitdiff
path: root/src/cpu/x86/16bit
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/x86/16bit')
-rw-r--r--src/cpu/x86/16bit/entry16.inc124
-rw-r--r--src/cpu/x86/16bit/entry16.lds2
-rw-r--r--src/cpu/x86/16bit/reset16.inc21
-rw-r--r--src/cpu/x86/16bit/reset16.lds14
4 files changed, 161 insertions, 0 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
new file mode 100644
index 0000000000..61726d8ad9
--- /dev/null
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -0,0 +1,124 @@
+/*
+This software and ancillary information (herein called SOFTWARE )
+called LinuxBIOS is made available under the terms described
+here. The SOFTWARE has been approved for release with associated
+LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
+been authored by an employee or employees of the University of
+California, operator of the Los Alamos National Laboratory under
+Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
+U.S. Government has rights to use, reproduce, and distribute this
+SOFTWARE. The public may copy, distribute, prepare derivative works
+and publicly display this SOFTWARE without charge, provided that this
+Notice and any statement of authorship are reproduced on all copies.
+Neither the Government nor the University makes any warranty, express
+or implied, or assumes any liability or responsibility for the use of
+this SOFTWARE. If SOFTWARE is modified to produce derivative works,
+such modified SOFTWARE should be clearly marked, so as not to confuse
+it with the version available from LANL.
+ */
+/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
+ * rminnich@lanl.gov
+ */
+
+
+/** Start code to put an i386 or later processor into 32-bit
+ * protected mode.
+ */
+
+/* .section ".rom.text" */
+#include <arch/rom_segs.h>
+.code16
+.globl _start
+.type _start, @function
+
+_start:
+ cli
+ /* Save the BIST result */
+ movl %eax, %ebp
+
+/* thanks to kmliu@sis.tw.com for this TBL fix ... */
+/**/
+/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/
+/* any further code. Even though paging is disabled we could still get*/
+/*false address translations due to the TLB if we didn't invalidate it.*/
+/**/
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB*/
+
+
+ /* Invalidating the cache here seems to be a bad idea on
+ * modern processors. Don't.
+ * If we are hyperthreaded or we have multiple cores it is bad,
+ * for SMP startup. On Opterons it causes a 5 second delay.
+ * Invalidating the cache was pure paranoia in any event.
+ * If you cpu needs it you can write a cpu dependent version of
+ * entry16.inc.
+ */
+
+ /* Note: gas handles memory addresses in 16 bit code very poorly.
+ * In particular it doesn't appear to have a directive allowing you
+ * associate a section or even an absolute offset with a segment register.
+ *
+ * This means that anything except cs:ip relative offsets are
+ * a real pain in 16 bit mode. And explains why it is almost
+ * imposible to get gas to do lgdt correctly.
+ *
+ * One way to work around this is to have the linker do the
+ * math instead of the assembler. This solves the very
+ * pratical problem of being able to write code that can
+ * be relocated.
+ *
+ * An lgdt call before we have memory enabled cannot be
+ * position independent, as we cannot execute a call
+ * instruction to get our current instruction pointer.
+ * So while this code is relocateable it isn't arbitrarily
+ * relocatable.
+ *
+ * The criteria for relocation have been relaxed to their
+ * utmost, so that we can use the same code for both
+ * our initial entry point and startup of the second cpu.
+ * The code assumes when executing at _start that:
+ * (((cs & 0xfff) == 0) and (ip == _start & 0xffff))
+ * or
+ * ((cs == anything) and (ip == 0)).
+ *
+ * The restrictions in reset16.inc mean that _start initially
+ * must be loaded at or above 0xffff0000 or below 0x100000.
+ *
+ * The linker scripts computs gdtptr16_offset by simply returning
+ * the low 16 bits. This means that the intial segment used
+ * when start is called must be 64K aligned. This should not
+ * restrict the address as the ip address can be anything.
+ */
+
+ movw %cs, %ax
+ shlw $4, %ax
+ movw $gdtptr16_offset, %bx
+ subw %ax, %bx
+ data32 lgdt %cs:(%bx)
+
+ movl %cr0, %eax
+ andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+ orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movl %eax, %cr0
+
+ /* Restore BIST to %eax */
+ movl %ebp, %eax
+
+ /* Now that we are in protected mode jump to a 32 bit code segment. */
+ data32 ljmp $ROM_CODE_SEG, $__protected_start
+
+/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
+ * at 0x18; these are Linux-compatible.
+ */
+
+.align 4
+.globl gdtptr16
+gdtptr16:
+ .word gdt_end - gdt -1 /* compute the table limit */
+ .long gdt /* we know the offset */
+
+.globl _estart
+_estart:
+ .code32
+
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds
new file mode 100644
index 0000000000..db37e66302
--- /dev/null
+++ b/src/cpu/x86/16bit/entry16.lds
@@ -0,0 +1,2 @@
+ gdtptr16_offset = gdtptr16 & 0xffff;
+ _start_offset = _start & 0xffff;
diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc
new file mode 100644
index 0000000000..d36c94085e
--- /dev/null
+++ b/src/cpu/x86/16bit/reset16.inc
@@ -0,0 +1,21 @@
+ .section ".reset"
+ .code16
+.globl reset_vector
+reset_vector:
+#if _ROMBASE >= 0xffff0000
+ /* jmp _start */
+ .byte 0xe9
+ .int _start - ( . + 2 )
+ /* Note: The above jump is hand coded to work around bugs in binutils.
+ * 5 byte are used for a 3 byte instruction. This works because x86
+ * is little endian and allows us to use supported 32bit relocations
+ * instead of the weird 16 bit relocations that binutils does not
+ * handle consistenly between versions because they are used so rarely.
+ */
+#else
+# error _ROMBASE is an unsupported value
+#endif
+ . = 0x8;
+ .code32
+ jmp protected_start
+ .previous
diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds
new file mode 100644
index 0000000000..80f2fc0c6f
--- /dev/null
+++ b/src/cpu/x86/16bit/reset16.lds
@@ -0,0 +1,14 @@
+/*
+ * _ROMTOP : The top of the rom used where we
+ * need to put the reset vector.
+ */
+
+SECTIONS {
+ _ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
+ . = _ROMTOP;
+ .reset . : {
+ *(.reset)
+ . = 15 ;
+ BYTE(0x00);
+ }
+}