diff options
Diffstat (limited to 'src/cpu/via')
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 18 | ||||
| -rw-r--r-- | src/cpu/via/model_c3/model_c3_init.c | 2 | ||||
| -rw-r--r-- | src/cpu/via/model_c7/model_c7_init.c | 6 |
3 files changed, 13 insertions, 13 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 8a12c8fa48..8bc274b381 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -179,12 +179,12 @@ testok: movb $0x40,%al pushl %eax /* bist */ call main - /* + /* * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we * get STACK up, we restore that. It is only needed if we * want to go back. */ - + /* We don't need cache as ram for now on */ /* disable cache */ movl %cr0, %eax @@ -207,7 +207,7 @@ testok: movb $0x40,%al movl $(0 | 6), %eax //movl $(0 | MTRR_TYPE_WRBACK), %eax wrmsr - + /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; * If 1M cacheable, then when S3 resume, there is stange color on * screen for 2 sec. suppose problem of a0000-dfffff and cache. @@ -218,7 +218,7 @@ testok: movb $0x40,%al movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax wrmsr - + movl $0x202, %ecx xorl %edx, %edx movl $(0x80000 | 6), %eax @@ -229,7 +229,7 @@ testok: movb $0x40,%al movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax wrmsr - + movl $0x204, %ecx xorl %edx, %edx movl $(0xc0000 | 6), %eax @@ -239,8 +239,8 @@ testok: movb $0x40,%al movl $0x205, %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax - wrmsr - + wrmsr + /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ movl $0x206, %ecx xorl %edx, %edx @@ -267,7 +267,7 @@ testok: movb $0x40,%al __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -275,7 +275,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c index ef979198da..291e4afef9 100644 --- a/src/cpu/via/model_c3/model_c3_init.c +++ b/src/cpu/via/model_c3/model_c3_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c index da946957c2..5474b8d6c7 100644 --- a/src/cpu/via/model_c7/model_c7_init.c +++ b/src/cpu/via/model_c7/model_c7_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -36,7 +36,7 @@ #define MSR_IA32_MISC_ENABLE 0x000001a0 static int c7a_speed_translation[] = { -// LFM HFM +// LFM HFM 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V @@ -51,7 +51,7 @@ static int c7a_speed_translation[] = { }; static int c7d_speed_translation[] = { -// LFM HFM +// LFM HFM 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V |