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path: root/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
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Diffstat (limited to 'src/cpu/samsung/exynos5250/dmc_init_ddr3.c')
-rw-r--r--src/cpu/samsung/exynos5250/dmc_init_ddr3.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index e3d46ab2d5..f2c228d339 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -158,8 +158,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Send PALL command */
dmc_config_prech(mem, dmc);
- /* Send NOP, MRS and ZQINIT commands */
- dmc_config_mrs(mem, dmc);
+ if (mem_reset) {
+ /* Send NOP, MRS and ZQINIT commands.
+ * Sending MRS command will reset the DRAM. We should not be
+ * reseting the DRAM after resume, this will lead to memory
+ * corruption as DRAM content is lost after DRAM reset
+ */
+ dmc_config_mrs(mem, dmc);
+ }
if (mem->gate_leveling_enable) {
val = PHY_CON0_RESET_VAL;