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-rw-r--r--src/cpu/ppc/mpc74xx/Config.lb14
-rw-r--r--src/cpu/ppc/mpc74xx/mpc74xx.inc8
-rw-r--r--src/cpu/ppc/ppc4xx/Config.lb14
-rw-r--r--src/cpu/ppc/ppc4xx/cache.S6
-rw-r--r--src/cpu/ppc/ppc4xx/pci_domain.c2
-rw-r--r--src/cpu/ppc/ppc4xx/ppc4xx.inc8
-rw-r--r--src/cpu/ppc/ppc4xx/sdram.c8
-rw-r--r--src/cpu/ppc/ppc7xx/Config.lb14
-rw-r--r--src/cpu/ppc/ppc7xx/ppc7xx.inc14
-rw-r--r--src/cpu/ppc/ppc970/Config.lb6
10 files changed, 47 insertions, 47 deletions
diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb
index ee65e41f3b..86ce6faa44 100644
--- a/src/cpu/ppc/mpc74xx/Config.lb
+++ b/src/cpu/ppc/mpc74xx/Config.lb
@@ -1,19 +1,19 @@
##
## CPU initialization
##
-uses _RAMBASE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
##
## Use cache ram for initial setup
##
-default USE_DCACHE_RAM=1
+default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
-default DCACHE_RAM_BASE=_RAMBASE+0x100000
+default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 32Kb
-default DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_SIZE=0x8000
initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
object cache.S
diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index ba2c0018d5..0a3bfe8a09 100644
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -30,7 +30,7 @@
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
- * - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
+ * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
@@ -147,7 +147,7 @@
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
- * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
+ * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -156,8 +156,8 @@
mtibatl 0, r2
isync
- lis r2, _ROMBASE@h
-#if ROM_SIZE > 1048576
+ lis r2, CONFIG_ROMBASE@h
+#if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb
index f739495325..0b6f6233bb 100644
--- a/src/cpu/ppc/ppc4xx/Config.lb
+++ b/src/cpu/ppc/ppc4xx/Config.lb
@@ -1,19 +1,19 @@
##
## CPU initialization
##
-uses _RAMBASE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
##
## PPC4XX always uses cache ram for initial setup
##
-default USE_DCACHE_RAM=1
+default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
-default DCACHE_RAM_BASE=_RAMBASE+0x100000
+default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb
-default DCACHE_RAM_SIZE=16384
+default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
initobject cache.S
diff --git a/src/cpu/ppc/ppc4xx/cache.S b/src/cpu/ppc/ppc4xx/cache.S
index 3f69b949d2..501be9a174 100644
--- a/src/cpu/ppc/ppc4xx/cache.S
+++ b/src/cpu/ppc/ppc4xx/cache.S
@@ -57,7 +57,7 @@ invalidate_icache:
invalidate_dcache:
li r6,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
- li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
+ li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
1:
@@ -79,8 +79,8 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
- li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
- li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
+ li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
+ li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
mtctr r10
li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
diff --git a/src/cpu/ppc/ppc4xx/pci_domain.c b/src/cpu/ppc/ppc4xx/pci_domain.c
index f53446dc88..b0da1f0263 100644
--- a/src/cpu/ppc/ppc4xx/pci_domain.c
+++ b/src/cpu/ppc/ppc4xx/pci_domain.c
@@ -47,7 +47,7 @@ static void pci_domain_set_resources(device_t dev)
{
int idx = 3; /* who knows? */
- ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10);
+ ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10);
assign_resources(&dev->link[0]);
}
diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc
index e3943d130f..b5833ea4bc 100644
--- a/src/cpu/ppc/ppc4xx/ppc4xx.inc
+++ b/src/cpu/ppc/ppc4xx/ppc4xx.inc
@@ -94,15 +94,15 @@
isync
/*
- * Enable dcache region containing DCACHE_RAM_BASE
+ * Enable dcache region containing CONFIG_DCACHE_RAM_BASE
* On reset all regions are set to write-back, so we
* just leave them alone.
*
- * dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27))
+ * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27))
*/
- lis r4, DCACHE_RAM_BASE@ha
- ori r4, r4, DCACHE_RAM_BASE@l
+ lis r4, CONFIG_DCACHE_RAM_BASE@ha
+ ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
srwi r4, r4, 27
subfic r4, r4, 31
li r0, 1
diff --git a/src/cpu/ppc/ppc4xx/sdram.c b/src/cpu/ppc/ppc4xx/sdram.c
index 5068f9071f..f7a508b4fd 100644
--- a/src/cpu/ppc/ppc4xx/sdram.c
+++ b/src/cpu/ppc/ppc4xx/sdram.c
@@ -98,17 +98,17 @@ void memory_init(void)
/* TODO: work out why this trashes cache ram */
//mtsdram0(mem_mcopt1, 0x00000000);
-#if EMBEDDED_RAM_SIZE==128*1024*1024
+#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024
/* TODO */
-#elif EMBEDDED_RAM_SIZE==64*1024*1024
+#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024
set_sdram0(mem_sdtr1, TR);
set_sdram0(mem_mb0cf, B0CR);
set_sdram0(mem_rtr, RTR);
set_sdram0(mem_ecccf, ECCCF);
set_sdram0(mem_pmit, PMIT);
-#elif EMBEDDED_RAM_SIZE==32*1024*1024
+#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024
/* TODO */
-#elif EMBEDDED_RAM_SIZE==16*1024*1024
+#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024
/* TODO */
#endif
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb
index 521045b1bc..a04a777a06 100644
--- a/src/cpu/ppc/ppc7xx/Config.lb
+++ b/src/cpu/ppc/ppc7xx/Config.lb
@@ -1,19 +1,19 @@
##
## CPU initialization
##
-uses _RAMBASE
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
##
## PPC7XX always uses cache ram for initial setup
##
-default USE_DCACHE_RAM=1
+default CONFIG_USE_DCACHE_RAM=1
## Set dcache ram above coreboot image
-default DCACHE_RAM_BASE=_RAMBASE+0x100000
+default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
## Dcache size is 16Kb
-default DCACHE_RAM_SIZE=16384
+default CONFIG_DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
index bd599f324e..4f8ab86da3 100644
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc
@@ -30,7 +30,7 @@
* - enable L1 I/D caches, otherwise performance will be slow
* - set up DBATs for the following regions:
* - RAM (generally 0x00000000 -> 0x7fffffff)
- * - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
+ * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
* - I/O (generally 0xfc000000 -> 0xfdffffff)
* - the main purpose for setting up the DBATs is so the I/O region
* can be marked cache inhibited/write through
@@ -113,7 +113,7 @@
* IBATS
*
* IBAT0 covers RAM (0 -> 256Mb)
- * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
+ * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
*/
lis r2, 0@h
ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -122,8 +122,8 @@
mtibatl 0, r2
isync
- lis r2, _ROMBASE@h
-#if ROM_SIZE > 1048576
+ lis r2, CONFIG_ROMBASE@h
+#if CONFIG_ROM_SIZE > 1048576
ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
#else
ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
@@ -161,9 +161,9 @@
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
*/
- lis r1, DCACHE_RAM_BASE@h
- ori r1, r1, DCACHE_RAM_BASE@l
- li r3, (DCACHE_RAM_SIZE / 32)
+ lis r1, CONFIG_DCACHE_RAM_BASE@h
+ ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
+ li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32
diff --git a/src/cpu/ppc/ppc970/Config.lb b/src/cpu/ppc/ppc970/Config.lb
index 60da7f2b71..4eebe71bb7 100644
--- a/src/cpu/ppc/ppc970/Config.lb
+++ b/src/cpu/ppc/ppc970/Config.lb
@@ -1,15 +1,15 @@
##
## CPU initialization
##
-uses _RAMBASE
-uses USE_DCACHE_RAM
+uses CONFIG_RAMBASE
+uses CONFIG_USE_DCACHE_RAM
##
## Assumes RAM already initialiazed
## This is true for the Apache board, but may
## not be for other 970 systems.
##
-default USE_DCACHE_RAM=0
+default CONFIG_USE_DCACHE_RAM=0
initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 07:10:47 +0000