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-rw-r--r--src/cpu/ppc/ppc7xx/Config.lb27
-rw-r--r--src/cpu/ppc/ppc7xx/cache.S23
-rw-r--r--src/cpu/ppc/ppc7xx/clock.c27
-rw-r--r--src/cpu/ppc/ppc7xx/ppc7xx.inc170
4 files changed, 0 insertions, 247 deletions
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb
deleted file mode 100644
index a04a777a06..0000000000
--- a/src/cpu/ppc/ppc7xx/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## CPU initialization
-##
-uses CONFIG_RAMBASE
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-
-##
-## PPC7XX always uses cache ram for initial setup
-##
-default CONFIG_USE_DCACHE_RAM=1
-## Set dcache ram above coreboot image
-default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000
-## Dcache size is 16Kb
-default CONFIG_DCACHE_RAM_SIZE=16384
-
-initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc
-
-# Only TotalImpact Briq uses the ppc7xx and it brings its own clock.o
-# so we comment this out for now:
-# object clock.o
-object cache.S
-#initobject clock.o
-initobject cache.S
-
-dir /cpu/simple_init
diff --git a/src/cpu/ppc/ppc7xx/cache.S b/src/cpu/ppc/ppc7xx/cache.S
deleted file mode 100644
index 237b178bdf..0000000000
--- a/src/cpu/ppc/ppc7xx/cache.S
+++ /dev/null
@@ -1,23 +0,0 @@
-#define ASM
-#include "ppcreg.h"
-#include <ppc_asm.tmpl>
-
-#define NUM_CACHE_LINES 128*8
-#define L1_CACHE_LINE_SIZE 32
-#define cache_flush_buffer 0x1000
-
-/*
- * Flush data cache
- * Do this by just reading lots of stuff into the cache.
- */
-.globl flush_dcache
-flush_dcache:
- lis r3,cache_flush_buffer@h
- ori r3,r3,cache_flush_buffer@l
- li r4,NUM_CACHE_LINES
- mtctr r4
-0: lwz r4,0(r3)
- addi r3,r3,L1_CACHE_LINE_SIZE
- bdnz 0b
- blr
-
diff --git a/src/cpu/ppc/ppc7xx/clock.c b/src/cpu/ppc/ppc7xx/clock.c
deleted file mode 100644
index bb600c6d5b..0000000000
--- a/src/cpu/ppc/ppc7xx/clock.c
+++ /dev/null
@@ -1,27 +0,0 @@
-#include <ppc.h>
-
-static int PLL_multiplier[] = {
- 25, /* 0000 - 2.5x */
- 75, /* 0001 - 7.5x */
- 70, /* 0010 - 7x */
- 10, /* 0011 - bypass */
- 20, /* 0100 - 2x */
- 65, /* 0101 - 6.5x */
- 100, /* 0110 - 10x */
- 45, /* 0111 - 4.5x */
- 30, /* 1000 - 3x */
- 55, /* 1001 - 5.5x */
- 40, /* 1010 - 4x */
- 50, /* 1011 - 5x */
- 80, /* 1100 - 8x */
- 60, /* 1101 - 6x */
- 35, /* 1110 - 3.5x */
- 0, /* 1111 - off */
-};
-
-unsigned long
-get_timer_freq(void)
-{
- unsigned long clock = CONFIG_SYS_CLK_FREQ * 1000000;
- return clock * PLL_multiplier[ppc_gethid1() >> 28] / 10;
-}
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
deleted file mode 100644
index 4f8ab86da3..0000000000
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * The aim of this code is to bring the machine from power-on to the point
- * where we can jump to the the main coreboot entry point hardwaremain()
- * which is written in C.
- *
- * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
- * out of ROM, generally at 0xfff00100.
- *
- * Before we jump to harwaremain() we want to do the following:
- *
- * - enable L1 I/D caches, otherwise performance will be slow
- * - set up DBATs for the following regions:
- * - RAM (generally 0x00000000 -> 0x7fffffff)
- * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE)
- * - I/O (generally 0xfc000000 -> 0xfdffffff)
- * - the main purpose for setting up the DBATs is so the I/O region
- * can be marked cache inhibited/write through
- * - set up IBATs for RAM and ROM
- *
- */
-
-#include <ppc750.h>
-
-#define BSP_IOREGION1 0x80000000
-#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
-#define BSP_IOREGION2 0xFD000000
-#define BSP_IOMASK2 BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
-
- isync
-
- /*
- * Disable dcache and MMU, so we're in a known state
- */
- li r0, 0
- sync
- mtspr HID0, r0
- sync
- mtmsr r0
- isync
-
- /*
- * Invalidate D & I BATS
- */
- mtibatu 0, r0
- mtibatu 1, r0
- mtibatu 2, r0
- mtibatu 3, r0
- isync
- mtdbatu 0, r0
- mtdbatu 1, r0
- mtdbatu 2, r0
- mtdbatu 3, r0
- isync
-
- /*
- * Clear segment registers (coreboot doesn't use these)
- */
- li r3, 15
-1: mtsrin r3, r0
- subic. r3, r3, 1
- bge 1b
- isync
-
- /*
- * Set up DBATs
- *
- * DBAT0 covers RAM (0 -> 0x0FFFFFFF) (256Mb)
- * DBAT1 covers PCI memory and ROM (0xFD000000 -> 0xFFFFFFFF) (64Mb)
- * DBAT2 covers PCI memory (0x80000000 -> 0x8FFFFFFF) (256Mb)
- * DBAT3 is not used
- */
- lis r2, 0@h
- ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
- ori r2, r2, BAT_READ_WRITE | BAT_GUARDED
- mtdbatu 0, r3
- mtdbatl 0, r2
- isync
-
- lis r2, BSP_IOREGION2@h
- ori r3, r2, BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
- ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
- mtdbatu 1, r3
- mtdbatl 1, r2
- isync
-
- lis r2, BSP_IOREGION1@h
- ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
- ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
- mtdbatu 2, r3
- mtdbatl 2, r2
- isync
-
- /*
- * IBATS
- *
- * IBAT0 covers RAM (0 -> 256Mb)
- * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE)
- */
- lis r2, 0@h
- ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
- ori r2, r2, BAT_READ_WRITE
- mtibatu 0, r3
- mtibatl 0, r2
- isync
-
- lis r2, CONFIG_ROMBASE@h
-#if CONFIG_ROM_SIZE > 1048576
- ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
-#else
- ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
-#endif
- ori r2, r2, BAT_READ_ONLY
- mtibatu 1, r3
- mtibatl 1, r2
- isync
-
- /*
- * Enable MMU
- */
- mfmsr r2
- ori r2, r2, MSR_DR | MSR_IR
- mtmsr r2
- isync
- sync
-
- /*
- * Enable and invalidate the L1 icache
- */
- mfspr r2, HID0
- ori r2, r2, HID0_ICE | HID0_ICFI
- isync
- mtspr HID0, r2
- /*
- * Enable and invalidate the L1 dcache
- */
- mfspr r2, HID0
- ori r2, r2, HID0_DCE | HID0_DCFI
- sync
- mtspr HID0, r2
-
- /*
- * Initialize data cache blocks
- * (assumes cache block size of 32 bytes)
- */
- lis r1, CONFIG_DCACHE_RAM_BASE@h
- ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
- li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
- mtctr r3
-0: dcbz r0, r1
- addi r1, r1, 32
- bdnz 0b
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