diff options
Diffstat (limited to 'src/cpu/ppc/ppc4xx')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/Config.lb | 29 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/cache.S | 179 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/chip.h | 4 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/clock.c | 181 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/mem.c | 59 | ||||
| -rwxr-xr-x | src/cpu/ppc/ppc4xx/pci_bridge.c | 33 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/pci_domain.c | 53 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/ppc4xx.inc | 111 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/sdram.c | 133 |
9 files changed, 0 insertions, 782 deletions
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb deleted file mode 100644 index 0b6f6233bb..0000000000 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ /dev/null @@ -1,29 +0,0 @@ -## -## CPU initialization -## -uses CONFIG_RAMBASE -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE - -## -## PPC4XX always uses cache ram for initial setup -## -default CONFIG_USE_DCACHE_RAM=1 -## Set dcache ram above coreboot image -default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 -## Dcache size is 16Kb -default CONFIG_DCACHE_RAM_SIZE=16384 - -initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc -initobject cache.S -initobject sdram.c -initobject clock.c - -config chip.h -object clock.o -object cache.S -object pci_domain.o -driver pci_bridge.o - -dir /cpu/simple_init diff --git a/src/cpu/ppc/ppc4xx/cache.S b/src/cpu/ppc/ppc4xx/cache.S deleted file mode 100644 index 501be9a174..0000000000 --- a/src/cpu/ppc/ppc4xx/cache.S +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - */ - -#include <ppc_asm.tmpl> - -#define CACHELINE_SIZE 32 /* 32 bytes (8 words) */ - -/* - * Cache functions. - */ - .globl invalidate_icache -invalidate_icache: - iccci r0,r0 /* for 405, iccci invalidates the */ - blr /* entire I cache */ - - .globl invalidate_dcache -invalidate_dcache: - li r6,0x0000 /* clear GPR 6 */ - /* Do loop for # of dcache congruence classes. */ - li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -1: - dccci 0,r6 /* invalidate line */ - addi r6,r6, CACHELINE_SIZE /* bump to next line */ - bdnz 1b - blr - - .globl flush_dcache -flush_dcache: - lis r9,0x0002 /* set mask for EE and CE msr bits */ - ori r9,r9,0x8000 - mfmsr r12 /* save msr */ - andc r9,r12,r9 - mtmsr r9 /* disable EE and CE */ - li r10,0x0001 /* enable data cache for unused memory */ - mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ - or r10,r10,r9 /* bit 31 in dccr */ - mtdccr r10 - - /* do loop for # of congruence classes. */ - li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) - li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ - mtctr r10 - li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */ - add r11,r10,r11 /* add to get to other side of cache line */ -1: - lwz r3,0(r10) /* least recently used side */ - lwz r3,0(r11) /* the other side */ - dccci r0,r11 /* invalidate both sides */ - addi r10,r10,CACHELINE_SIZE /* bump to next line */ - addi r11,r11,CACHELINE_SIZE /* bump to next line */ - bdnz 1b - sync /* allow memory access to complete */ - mtdccr r9 /* restore dccr */ - mtmsr r12 /* restore msr */ - blr - - .globl icache_enable -icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - lis r3,0x8000 /* set bit 0 */ - mticcr r3 - blr - - .globl icache_disable -icache_disable: - lis r3,0x0000 /* clear bit 0 */ - mticcr r3 - isync - blr - - .globl icache_status -icache_status: - mficcr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - lis r3,0x8000 /* set bit 0 */ - mtdccr r3 - blr - - .globl dcache_disable -dcache_disable: - mflr r8 - bl flush_dcache - mtlr r8 - lis r3,0x0000 /* clear bit 0 */ - mtdccr r3 - blr - - .globl dcache_status -dcache_status: - mfdccr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - diff --git a/src/cpu/ppc/ppc4xx/chip.h b/src/cpu/ppc/ppc4xx/chip.h deleted file mode 100644 index 0171a4f9ef..0000000000 --- a/src/cpu/ppc/ppc4xx/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct cpu_ppc_ppc4xx_config -{ -}; -extern struct chip_operations cpu_ppc_ppc4xx_ops; diff --git a/src/cpu/ppc/ppc4xx/clock.c b/src/cpu/ppc/ppc4xx/clock.c deleted file mode 100644 index 0c6b465d65..0000000000 --- a/src/cpu/ppc/ppc4xx/clock.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc.h> -#include <ppc4xx.h> -#include <ppcreg.h> -#include <string.h> - -/* ------------------------------------------------------------------------- */ - -#define ONE_BILLION 1000000000 - -void get_sys_info (struct ppc4xx_sys_info * sysInfo) -{ - unsigned long pllmr; - unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ * 1000); - unsigned pvr = ppc_getpvr(); - unsigned long psr; - unsigned long m; - - memset(sysInfo, 0, sizeof(*sysInfo)); - - /* - * Read PLL Mode register - */ - pllmr = mfdcr(CPC0_PLLMR); - - /* - * Read Pin Strapping register - */ - psr = mfdcr(CPC0_PSR); - - /* - * Determine FWD_DIV. - */ - sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29); - - /* - * Determine FBK_DIV. - */ - sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25); - if (sysInfo->pllFbkDiv == 0) { - sysInfo->pllFbkDiv = 16; - } - - /* - * Determine PLB_DIV. - */ - sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1; - - /* - * Determine PCI_DIV. - */ - sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1; - - /* - * Determine EXTBUS_DIV. - */ - sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2; - - /* - * Determine OPB_DIV. - */ - sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1; - - /* - * Check if PPC405GPr used (mask minor revision field) - */ - if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - /* - * Determine FWD_DIV B (only PPC405GPr with new mode strapping). - */ - sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK); - - /* - * Determine factor m depending on PLL feedback clock source - */ - if (!(psr & PSR_PCI_ASYNC_EN)) { - if (psr & PSR_NEW_MODE_EN) { - /* - * sync pci clock used as feedback (new mode) - */ - m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv; - } else { - /* - * sync pci clock used as feedback (legacy mode) - */ - m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv; - } - } else if (psr & PSR_NEW_MODE_EN) { - if (psr & PSR_PERCLK_SYNC_MODE_EN) { - /* - * PerClk used as feedback (new mode) - */ - m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv; - } else { - /* - * CPU clock used as feedback (new mode) - */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; - } - } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) { - /* - * PerClk used as feedback (legacy mode) - */ - m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv; - } else { - /* - * PLB clock used as feedback (legacy mode) - */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv; - } - - sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs; - sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv; - sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) / - (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv); - } else { - /* - * Check pllFwdDiv to see if running in bypass mode where the CPU speed - * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO - * to make sure it is within the proper range. - * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV - * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. - */ - if (sysInfo->pllFwdDiv == 1) { - sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ * 1000000; - sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; - } else { - sysInfo->freqVCOMhz = ( 1000000 * - sysInfo->pllFwdDiv * - sysInfo->pllFbkDiv * - sysInfo->pllPlbDiv - ) / sysClkPeriodPs; - if (sysInfo->freqVCOMhz >= VCO_MIN - && sysInfo->freqVCOMhz <= VCO_MAX) { - sysInfo->freqPLB = (ONE_BILLION / - ((sysClkPeriodPs * 10) / - sysInfo->pllFbkDiv)) * 10000; - sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; - } - } - } -} - -unsigned long get_timer_freq(void) -{ - struct ppc4xx_sys_info sys_info; - - get_sys_info(&sys_info); - return sys_info.freqProcessor; -} - -unsigned long get_pci_bus_freq(void) -{ - struct ppc4xx_sys_info sys_info; - - get_sys_info(&sys_info); - return sys_info.freqPLB; -} diff --git a/src/cpu/ppc/ppc4xx/mem.c b/src/cpu/ppc/ppc4xx/mem.c deleted file mode 100644 index f1bd2f8b8e..0000000000 --- a/src/cpu/ppc/ppc4xx/mem.c +++ /dev/null @@ -1,59 +0,0 @@ -#include <ppc.h> -#include <mem.h> -#include <console/console.h> - -#define SDRAM0_CFGADDR 0x010 -#define SDRAM0_CFGDATA 0x011 - -#define SDRAM0_B0CR 0x40 -#define SDRAM0_B1CR 0x44 -#define SDRAM0_B2CR 0x48 -#define SDRAM0_B3CR 0x4C - -#define BA_MASK 0xffc00000 -#define BA_SHIFT 22 -#define SZ_MASK 0x000e0000 -#define SZ_SHIFT 17 -#define AM_MASK 0x0000e000 -#define AM_SHIFT 13 -#define BE_MASK 0x00000001 -#define BE_SHIFT 0 - -struct mem_range mem_bank[4]; - -void -getmemrange(int bank, unsigned int reg) -{ - unsigned int val; - unsigned int size; - - mtdcr(SDRAM0_CFGADDR, reg); - val = mfdcr(SDRAM0_CFGDATA); - - if ((val & BE_MASK) == 0) - { - mem_bank[bank].basek = 0; - mem_bank[bank].sizek = 0; - return; - } - - size = ((val & BA_MASK) >> BA_SHIFT); - mem_bank[bank].basek = size * 1024; - - size = 4 << ((val & SZ_MASK) >> SZ_SHIFT); - mem_bank[bank].sizek = size * 1024; - - printk_info("mem bank %d: basek %d, sizek %d\n", bank, mem_bank[bank].basek, mem_bank[bank].sizek); -} - -struct mem_range * -sizeram(void) -{ - getmemrange(0, SDRAM0_B0CR); - getmemrange(1, SDRAM0_B1CR); - getmemrange(2, SDRAM0_B2CR); - getmemrange(3, SDRAM0_B3CR); - - return mem_bank; -} - diff --git a/src/cpu/ppc/ppc4xx/pci_bridge.c b/src/cpu/ppc/ppc4xx/pci_bridge.c deleted file mode 100755 index 5c945c28eb..0000000000 --- a/src/cpu/ppc/ppc4xx/pci_bridge.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Initialisation of the PCI bridge . - */ - -#include <arch/io.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> - -static void -pci_bridge_enable(struct device *dev) -{ - printk_info("Configure PCI Bridge\n"); - - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); - pci_write_config16(dev, 0x60, 0x0f00); - - printk_info("PCI Bridge configuration complete\n"); -} - -struct device_operations pci_bridge_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = pci_bridge_enable, - .scan_bus = 0, -}; - -struct pci_driver pci_bridge_pci_driver __pci_driver = { - .ops = &pci_bridge_ops, - .device = PCI_DEVICE_ID_IBM_405GP, - .vendor = PCI_VENDOR_ID_IBM, -}; diff --git a/src/cpu/ppc/ppc4xx/pci_domain.c b/src/cpu/ppc/ppc4xx/pci_domain.c deleted file mode 100644 index 6b8b74f461..0000000000 --- a/src/cpu/ppc/ppc4xx/pci_domain.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Initialisation of the PCI bridge . - */ - -#include <arch/io.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> - -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void pci_domain_set_resources(device_t dev) -{ - int idx = 3; /* who knows? */ - - ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10); - assign_resources(&dev->link[0]); -} - -struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = &pci_ppc_conf1 -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - dev->ops = &pci_domain_ops; - } -} - -struct chip_operations cpu_ppc_ppc4xx_ops = { - CHIP_NAME("PPC 4XX CPU") - .enable_dev = enable_dev, -}; diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc deleted file mode 100644 index b5833ea4bc..0000000000 --- a/src/cpu/ppc/ppc4xx/ppc4xx.inc +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> - * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> - * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - */ - -/* - * Startup Code for IBM 4xx PowerPC based Embedded Boards - * - * Base on the U-Boot Startup Code - * - * The processor starts at 0xfffffffc and the code is executed - * from flash/rom. - * - * The purpose of this code is: - * - initalize the processor to a known state - * - turn on the I cache so things execute at a reasonable speed - * - set up a temporary stack in D cache - */ - -#include "ppc4xx.h" - - li r4,0x0000 - mtspr sgr,r4 - mtspr dcwr,r4 - mtesr r4 /* clear Exception Syndrome Reg */ - mttcr r4 /* clear Timer Control Reg */ - mtxer r4 /* clear Fixed-Point Exception Reg */ - mtevpr r4 /* clear Exception Vector Prefix Reg */ - li r4,0x1000 /* set ME bit (Machine Exceptions) */ - oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */ - mtmsr r4 /* change MSR */ - li r4,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */ - /* the dbsr is cleared by setting */ - /* bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - - /* - * Invalidate I and D caches. Enable I cache for defined memory - * regions to speed things up. Enable D cache for use as - * temporary memory until real memory is enabled. - */ - - bl invalidate_icache - bl invalidate_dcache - - /* - * Enable two 128MB cachable instruction regions - * - * 0x00000000 - 0x07FFFFFF - * 0xF8000000 - 0xFFFFFFFF - */ - - lis r4,0x8000 - ori r4,r4,0x0001 - mticcr r4 /* instruction cache enable */ - isync - - /* - * Enable dcache region containing CONFIG_DCACHE_RAM_BASE - * On reset all regions are set to write-back, so we - * just leave them alone. - * - * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27)) - */ - - lis r4, CONFIG_DCACHE_RAM_BASE@ha - ori r4, r4, CONFIG_DCACHE_RAM_BASE@l - srwi r4, r4, 27 - subfic r4, r4, 31 - li r0, 1 - slw r4, r0, r4 - mtdccr r4 /* data cache enable */ - sync diff --git a/src/cpu/ppc/ppc4xx/sdram.c b/src/cpu/ppc/ppc4xx/sdram.c deleted file mode 100644 index 17d07c769a..0000000000 --- a/src/cpu/ppc/ppc4xx/sdram.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <ppc_asm.tmpl> -#include <ppc.h> -#include <ppc4xx.h> -#include <timer.h> -#include <clock.h> -#include <stdint.h> - -#define CONFIGURE_SDRAM_BANK0 -#ifdef CONFIGURE_SDRAM_BANK0 - -/* - * According to the PPC405GPr Users Manual, only non-reserved - * bits of SDRAM registers can be set. This means reading the - * contents and masking off bits to be set. - */ -#define CMD_BITS 0x80C00000 -#define CMD_MASK 0xFFE00000 -#define TR_BITS 0x010E8016 -#define TR_MASK 0x018FC01F -#define B0CR_BITS 0x00084001 -#define B0CR_MASK 0xFFCEE001 -#define RTR_BITS 0x08080000 -#define RTR_MASK 0xFFFF0000 -#define ECCCF_BITS 0x00000000 -#define ECCCF_MASK 0x00F00000 -#define PMIT_BITS 0x0F000000 -#define PMIT_MASK 0xFFC00000 - -#define mfsdram0(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - -#define set_sdram0(reg, val) \ - mfsdram0(reg, reg32); \ - reg32 &= ~(val##_MASK); \ - reg32 |= (val##_BITS); \ - mtsdram0(reg, reg32) - -/*----------------------------------------------------------------------- - */ -void memory_init(void) -{ -#if 0 - unsigned long speed; - unsigned long sdtr1; -#endif - uint32_t reg32; - -#if 0 - /* - * Determine SDRAM speed - */ - speed = get_pci_bus_freq(); /* parameter not used on ppc4xx */ - - /* - * Support for 100MHz and 133MHz SDRAM - */ - if (speed > 100000000) { - /* - * 133 MHz SDRAM - */ - sdtr1 = 0x01074015; - rtr = 0x07f00000; - } else { - /* - * default: 100 MHz SDRAM - */ - sdtr1 = 0x0086400d; - rtr = 0x05f00000; - } -#endif - - /* - * Disable memory controller. - */ -/* TODO: work out why this trashes cache ram */ - //mtsdram0(mem_mcopt1, 0x00000000); - -#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024 - /* TODO */ -#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024 - set_sdram0(mem_sdtr1, TR); - set_sdram0(mem_mb0cf, B0CR); - set_sdram0(mem_rtr, RTR); - set_sdram0(mem_ecccf, ECCCF); - set_sdram0(mem_pmit, PMIT); -#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024 - /* TODO */ -#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024 - /* TODO */ -#endif - - /* - * Wait for 200us - */ - udelay(200); - - /* - * Set memory controller options reg, MCOPT1. - * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst - * read/prefetch. - */ - set_sdram0(mem_mcopt1, CMD); - - /* - * Wait for 10ms - */ - udelay(10000); -} - -#endif /* CONFIGURE_SDRAM_BANK0 */ |