diff options
Diffstat (limited to 'src/cpu/ppc/ppc4xx')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/Config.lb | 14 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/cache.S | 6 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/pci_domain.c | 2 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/ppc4xx.inc | 8 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/sdram.c | 8 |
5 files changed, 19 insertions, 19 deletions
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb index f739495325..0b6f6233bb 100644 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ b/src/cpu/ppc/ppc4xx/Config.lb @@ -1,19 +1,19 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE ## ## PPC4XX always uses cache ram for initial setup ## -default USE_DCACHE_RAM=1 +default CONFIG_USE_DCACHE_RAM=1 ## Set dcache ram above coreboot image -default DCACHE_RAM_BASE=_RAMBASE+0x100000 +default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 ## Dcache size is 16Kb -default DCACHE_RAM_SIZE=16384 +default CONFIG_DCACHE_RAM_SIZE=16384 initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc initobject cache.S diff --git a/src/cpu/ppc/ppc4xx/cache.S b/src/cpu/ppc/ppc4xx/cache.S index 3f69b949d2..501be9a174 100644 --- a/src/cpu/ppc/ppc4xx/cache.S +++ b/src/cpu/ppc/ppc4xx/cache.S @@ -57,7 +57,7 @@ invalidate_icache: invalidate_dcache: li r6,0x0000 /* clear GPR 6 */ /* Do loop for # of dcache congruence classes. */ - li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) + li r7,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) /* NOTE: dccci invalidates both */ mtctr r7 /* ways in the D cache */ 1: @@ -79,8 +79,8 @@ flush_dcache: mtdccr r10 /* do loop for # of congruence classes. */ - li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) - li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ + li r10,(CONFIG_DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) + li r11,(CONFIG_DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ mtctr r10 li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */ add r11,r10,r11 /* add to get to other side of cache line */ diff --git a/src/cpu/ppc/ppc4xx/pci_domain.c b/src/cpu/ppc/ppc4xx/pci_domain.c index f53446dc88..b0da1f0263 100644 --- a/src/cpu/ppc/ppc4xx/pci_domain.c +++ b/src/cpu/ppc/ppc4xx/pci_domain.c @@ -47,7 +47,7 @@ static void pci_domain_set_resources(device_t dev) { int idx = 3; /* who knows? */ - ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10); + ram_resource(dev, idx, 0, CONFIG_EMBEDDED_RAM_SIZE>>10); assign_resources(&dev->link[0]); } diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc index e3943d130f..b5833ea4bc 100644 --- a/src/cpu/ppc/ppc4xx/ppc4xx.inc +++ b/src/cpu/ppc/ppc4xx/ppc4xx.inc @@ -94,15 +94,15 @@ isync /* - * Enable dcache region containing DCACHE_RAM_BASE + * Enable dcache region containing CONFIG_DCACHE_RAM_BASE * On reset all regions are set to write-back, so we * just leave them alone. * - * dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27)) + * dccr = (1 << (0x1F - (CONFIG_DCACHE_RAM_BASE >> 27)) */ - lis r4, DCACHE_RAM_BASE@ha - ori r4, r4, DCACHE_RAM_BASE@l + lis r4, CONFIG_DCACHE_RAM_BASE@ha + ori r4, r4, CONFIG_DCACHE_RAM_BASE@l srwi r4, r4, 27 subfic r4, r4, 31 li r0, 1 diff --git a/src/cpu/ppc/ppc4xx/sdram.c b/src/cpu/ppc/ppc4xx/sdram.c index 5068f9071f..f7a508b4fd 100644 --- a/src/cpu/ppc/ppc4xx/sdram.c +++ b/src/cpu/ppc/ppc4xx/sdram.c @@ -98,17 +98,17 @@ void memory_init(void) /* TODO: work out why this trashes cache ram */ //mtsdram0(mem_mcopt1, 0x00000000); -#if EMBEDDED_RAM_SIZE==128*1024*1024 +#if CONFIG_EMBEDDED_RAM_SIZE==128*1024*1024 /* TODO */ -#elif EMBEDDED_RAM_SIZE==64*1024*1024 +#elif CONFIG_EMBEDDED_RAM_SIZE==64*1024*1024 set_sdram0(mem_sdtr1, TR); set_sdram0(mem_mb0cf, B0CR); set_sdram0(mem_rtr, RTR); set_sdram0(mem_ecccf, ECCCF); set_sdram0(mem_pmit, PMIT); -#elif EMBEDDED_RAM_SIZE==32*1024*1024 +#elif CONFIG_EMBEDDED_RAM_SIZE==32*1024*1024 /* TODO */ -#elif EMBEDDED_RAM_SIZE==16*1024*1024 +#elif CONFIG_EMBEDDED_RAM_SIZE==16*1024*1024 /* TODO */ #endif |