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Diffstat (limited to 'src/cpu/p6/earlymtrr.c')
-rw-r--r--src/cpu/p6/earlymtrr.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/p6/earlymtrr.c b/src/cpu/p6/earlymtrr.c
index c4563ea860..707923b231 100644
--- a/src/cpu/p6/earlymtrr.c
+++ b/src/cpu/p6/earlymtrr.c
@@ -37,7 +37,7 @@ static void early_mtrr_init(void)
const unsigned long *msr_addr;
unsigned long cr0;
- print_err("Disabling cache\n");
+ print_err("Disabling cache\r\n");
/* Just to be sure, take all the steps to disable the cache.
* This may not be needed, but C3's may...
* Invalidate the cache */
@@ -56,7 +56,7 @@ static void early_mtrr_init(void)
/* Invalidate the cache again */
asm volatile ("invd");
- print_err("Clearing mtrr\n");
+ print_err("Clearing mtrr\r\n");
/* Inialize all of the relevant msrs to 0 */
msr.lo = 0;
@@ -81,7 +81,7 @@ static void early_mtrr_init(void)
wrmsr(0x201, msr);
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
- print_err("Setting XIP\n");
+ print_err("Setting XIP\r\n");
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
@@ -104,5 +104,5 @@ static void early_mtrr_init(void)
cr0 = read_cr0();
cr0 &= 0x9fffffff;
write_cr0(cr0);
- print_err("Enabled the cache\n");
+ print_err("Enabled the cache\r\n");
}