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-rw-r--r--src/cpu/intel/haswell/chip.h5
-rw-r--r--src/cpu/intel/model_2065x/chip.h5
-rw-r--r--src/cpu/intel/model_206ax/chip.h5
3 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index 5f2324ca37..02f2f1ce7f 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -1,5 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __CPU_INTEL_HASWELL_CHIP_H__
+#define __CPU_INTEL_HASWELL_CHIP_H__
+
#include <stdbool.h>
#include <stdint.h>
@@ -35,3 +38,5 @@ struct cpu_intel_haswell_config {
/* Enable S0iX support */
bool s0ix_enable;
};
+
+#endif /* __CPU_INTEL_HASWELL_CHIP_H__ */
diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h
index 9e89793d80..90921f746b 100644
--- a/src/cpu/intel/model_2065x/chip.h
+++ b/src/cpu/intel/model_2065x/chip.h
@@ -1,5 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __CPU_INTEL_MODEL_2065X_CHIP_H__
+#define __CPU_INTEL_MODEL_2065X_CHIP_H__
+
struct cpu_intel_model_2065x_config {
int tcc_offset; /* TCC Activation Offset */
};
+
+#endif /* __CPU_INTEL_MODEL_2065X_CHIP_H__ */
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
index 13cf3163e0..57e145eaf5 100644
--- a/src/cpu/intel/model_206ax/chip.h
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -1,5 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __CPU_INTEL_MODEL_206AX_CHIP_H__
+#define __CPU_INTEL_MODEL_206AX_CHIP_H__
+
/* Keep this in sync with acpi.c */
enum cpu_acpi_level {
CPU_ACPI_DISABLED = 0,
@@ -18,3 +21,5 @@ struct cpu_intel_model_206ax_config {
int tcc_offset; /* TCC Activation Offset */
};
+
+#endif /* __CPU_INTEL_MODEL_206AX_CHIP_H__ */