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-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S16
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S16
-rw-r--r--src/cpu/intel/car/non-evict/exit_car.S6
-rw-r--r--src/cpu/intel/car/p3/cache_as_ram.S16
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S30
-rw-r--r--src/cpu/intel/car/p4-netburst/exit_car.S6
6 files changed, 45 insertions, 45 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 316b703271..9c60308b28 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -29,7 +29,7 @@ wait_for_sipi:
bt $12, %eax
jc wait_for_sipi
- post_code(POST_SOC_CLEAR_FIXED_MTRRS)
+ post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list, %ebx
@@ -59,7 +59,7 @@ clear_var_mtrr:
dec %ebx
jnz clear_var_mtrr
- post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+ post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
@@ -84,7 +84,7 @@ addrsize_set_high:
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
- post_code(POST_SOC_SET_MTRR_BASE)
+ post_code(POSTCODE_SOC_SET_MTRR_BASE)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
movl $_car_mtrr_start, %eax
@@ -92,7 +92,7 @@ addrsize_set_high:
xorl %edx, %edx
wrmsr
- post_code(POST_SOC_SET_MTRR_MASK)
+ post_code(POSTCODE_SOC_SET_MTRR_MASK)
/* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
@@ -100,7 +100,7 @@ addrsize_set_high:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_MTRRS)
+ post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -128,7 +128,7 @@ addrsize_set_high:
shr $2, %ecx
rep stosl
- post_code(POST_SOC_DISABLE_CACHE)
+ post_code(POSTCODE_SOC_DISABLE_CACHE)
/* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -147,7 +147,7 @@ addrsize_set_high:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_CACHE)
+ post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -181,7 +181,7 @@ addrsize_set_high:
#endif
before_c_entry:
- post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
call bootblock_c_entry_bist
/* Should never see this postcode */
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 187b1ca9e2..18ac07036e 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -34,14 +34,14 @@ wait_for_sipi:
bt $12, %eax
jc wait_for_sipi
- post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+ post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Clean-up MTRR_DEF_TYPE_MSR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %eax, %eax
xorl %edx, %edx
wrmsr
- post_code(POST_SOC_CLEAR_FIXED_MTRRS)
+ post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list, %ebx
xor %eax, %eax
@@ -88,7 +88,7 @@ addrsize_set_high:
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
- post_code(POST_SOC_SET_MTRR_BASE)
+ post_code(POSTCODE_SOC_SET_MTRR_BASE)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
movl car_mtrr_start, %eax
@@ -96,7 +96,7 @@ addrsize_set_high:
xorl %edx, %edx
wrmsr
- post_code(POST_SOC_SET_MTRR_MASK)
+ post_code(POSTCODE_SOC_SET_MTRR_MASK)
/* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
@@ -117,7 +117,7 @@ addrsize_set_high:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_MTRRS)
+ post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -188,7 +188,7 @@ end_microcode_update:
orl $3, %eax
wrmsr
- post_code(POST_SOC_DISABLE_CACHE)
+ post_code(POSTCODE_SOC_DISABLE_CACHE)
/* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -199,7 +199,7 @@ end_microcode_update:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_CACHE)
+ post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -234,7 +234,7 @@ end_microcode_update:
#endif
before_c_entry:
- post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
call bootblock_c_entry_bist
/* Should never see this postcode */
diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S
index 56370f8841..9e37b4644c 100644
--- a/src/cpu/intel/car/non-evict/exit_car.S
+++ b/src/cpu/intel/car/non-evict/exit_car.S
@@ -13,14 +13,14 @@
chipset_teardown_car:
pop %esp
- post_code(POST_POSTCAR_DISABLE_CACHE)
+ post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
/* Disable cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
- post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
+ post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
/* Disable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -36,7 +36,7 @@ chipset_teardown_car:
andl $~1, %eax
wrmsr
- post_code(POST_POSTCAR_TEARDOWN_DONE)
+ post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
/* Return to caller. */
jmp *%esp
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 1431d323e6..779dbcca8a 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -42,7 +42,7 @@ clear_var_mtrr:
inc %ecx
dec %ebx
jnz clear_var_mtrr
- post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+ post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -50,7 +50,7 @@ clear_var_mtrr:
andl $(~0x00000cff), %eax
wrmsr
- post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
+ post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
movl $1, %eax
@@ -68,7 +68,7 @@ addrsize_set_high:
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
- post_code(POST_SOC_SET_CAR_BASE)
+ post_code(POSTCODE_SOC_SET_CAR_BASE)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
@@ -84,7 +84,7 @@ addrsize_set_high:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_MTRRS)
+ post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -92,7 +92,7 @@ addrsize_set_high:
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
- post_code(POST_SOC_ENABLE_CACHE)
+ post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax
@@ -114,7 +114,7 @@ addrsize_set_high:
xorl %eax, %eax
rep stosl
- post_code(POST_SOC_DISABLE_CACHE)
+ post_code(POSTCODE_SOC_DISABLE_CACHE)
/* Enable Cache-as-RAM mode by disabling cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -133,7 +133,7 @@ addrsize_set_high:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_FILL_CACHE)
+ post_code(POSTCODE_SOC_FILL_CACHE)
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -156,7 +156,7 @@ addrsize_set_high:
pushl %eax /* tsc[31:0] */
before_c_entry:
- post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
call bootblock_c_entry_bist
/* Should never see this postcode */
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 0362d104fa..9f514ef592 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -54,7 +54,7 @@ clear_var_mtrr:
inc %ecx
dec %ebx
jnz clear_var_mtrr
- post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+ post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
/* Configure the default memory type to uncacheable. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -62,7 +62,7 @@ clear_var_mtrr:
andl $(~0x00000cff), %eax
wrmsr
- post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
+ post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
/* Determine CPU_ADDR_BITS and load PHYSMASK high
* word to %edx.
@@ -106,7 +106,7 @@ addrsize_set_high:
bsp_init:
- post_code(POST_SOC_BSP_INIT)
+ post_code(POSTCODE_SOC_BSP_INIT)
/* Send INIT IPI to all excluding ourself. */
movl LAPIC(ICR), %edi
@@ -120,7 +120,7 @@ bsp_init:
andl $LAPIC_ICR_BUSY, %ecx
jnz 1b
- post_code(POST_SOC_COUNT_CORES)
+ post_code(POSTCODE_SOC_COUNT_CORES)
movl $1, %eax
cpuid
@@ -155,7 +155,7 @@ cores_counted:
hyper_threading_cpu:
- post_code(POST_SOC_CPU_HYPER_THREADING)
+ post_code(POSTCODE_SOC_CPU_HYPER_THREADING)
/* Send Start IPI to all excluding ourself. */
movl LAPIC(ICR), %edi
@@ -170,7 +170,7 @@ hyper_threading_cpu:
andl $LAPIC_ICR_BUSY, %ecx
jnz 1b
- post_code(POST_SOC_CPU_SIBLING_DELAY)
+ post_code(POSTCODE_SOC_CPU_SIBLING_DELAY)
/* Wait for sibling CPU to start. */
1: movl $(MTRR_PHYS_BASE(0)), %ecx
@@ -186,14 +186,14 @@ hyper_threading_cpu:
ap_init:
- post_code(POST_SOC_CPU_AP_INIT)
+ post_code(POSTCODE_SOC_CPU_AP_INIT)
/* Do not disable cache (so BSP can enable it). */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
- post_code(POST_SOC_SET_MTRR_BASE)
+ post_code(POSTCODE_SOC_SET_MTRR_BASE)
/* MTRR registers are shared between HT siblings. */
movl $(MTRR_PHYS_BASE(0)), %ecx
@@ -201,7 +201,7 @@ ap_init:
xorl %edx, %edx
wrmsr
- post_code(POST_SOC_AP_HALT)
+ post_code(POSTCODE_SOC_AP_HALT)
ap_halt:
cli
@@ -212,7 +212,7 @@ ap_halt:
sipi_complete:
- post_code(POST_SOC_SET_CAR_BASE)
+ post_code(POSTCODE_SOC_SET_CAR_BASE)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
@@ -228,7 +228,7 @@ sipi_complete:
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
- post_code(POST_SOC_ENABLE_MTRRS)
+ post_code(POSTCODE_SOC_ENABLE_MTRRS)
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -271,7 +271,7 @@ has_msr_11e:
wrmsr
no_msr_11e:
- post_code(POST_SOC_ENABLE_CACHE)
+ post_code(POSTCODE_SOC_ENABLE_CACHE)
/* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx
@@ -298,7 +298,7 @@ no_msr_11e:
jmp update_bsp_microcode
end_microcode_update:
#endif
- post_code(POST_SOC_DISABLE_CACHE)
+ post_code(POSTCODE_SOC_DISABLE_CACHE)
/* Disable caching to change MTRR's. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -338,7 +338,7 @@ cache_rom:
wrmsr
fill_cache:
- post_code(POST_SOC_FILL_CACHE)
+ post_code(POSTCODE_SOC_FILL_CACHE)
/* Enable cache. */
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -381,7 +381,7 @@ fill_cache:
#endif
before_c_entry:
- post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
call bootblock_c_entry_bist
/* Should never see this postcode */
diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S
index 1684407e81..05f77516c3 100644
--- a/src/cpu/intel/car/p4-netburst/exit_car.S
+++ b/src/cpu/intel/car/p4-netburst/exit_car.S
@@ -11,14 +11,14 @@
chipset_teardown_car:
pop %esp
- post_code(POST_POSTCAR_DISABLE_CACHE)
+ post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
/* Disable cache. */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
- post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
+ post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
/* Disable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
@@ -26,7 +26,7 @@ chipset_teardown_car:
andl $(~MTRR_DEF_TYPE_EN), %eax
wrmsr
- post_code(POST_POSTCAR_TEARDOWN_DONE)
+ post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
/* Return to caller. */
jmp *%esp
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 05:04:45 +0000