3 files changed, 15 insertions, 31 deletions

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 1f028c3f3f..a53978d012 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -164,28 +164,22 @@ static void generate_T_state_entries(int core, int cores_per_package)
 			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }
 
-static bool is_s0ix_enabled(void)
+static bool is_s0ix_enabled(const struct device *dev)
 {
 	if (!haswell_is_ult())
 		return false;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-
-	if (!lapic || !lapic->chip_info)
-		return false;
-
-	const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
+	const struct cpu_intel_haswell_config *conf = dev->chip_info;
 	return conf->s0ix_enable;
 }
 
-static void generate_C_state_entries(void)
+static void generate_C_state_entries(const struct device *dev)
 {
 	acpi_cstate_t acpi_cstate_map[3] = {0};
 
 	const int *acpi_cstates;
 
-	if (is_s0ix_enabled())
+	if (is_s0ix_enabled(dev))
 		acpi_cstates = cstate_set_s0ix;
 	else if (haswell_is_ult())
 		acpi_cstates = cstate_set_lp;
@@ -352,7 +346,7 @@ void generate_cpu_entries(const struct device *device)
 				coreID - 1, cores_per_package);
 
 			/* Generate C-state tables */
-			generate_C_state_entries();
+			generate_C_state_entries(device);
 
 			/* Generate T-state tables */
 			generate_T_state_entries(
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index 776e23903b..5f2324ca37 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Magic value used to locate this chip in the device tree */
-#define SPEEDSTEP_APIC_MAGIC 0xACAC
-
 #include <stdbool.h>
 #include <stdint.h>
 
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 7b3f3ad6cf..5a0b09d92e 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -172,18 +172,16 @@ static int pcode_mailbox_write(u32 command, u32 data)
 	return 0;
 }
 
+static struct device *cpu_cluster;
+
 static void initialize_vr_config(void)
 {
 	struct cpu_vr_config vr_config = { 0 };
 	msr_t msr;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-
-	if (lapic && lapic->chip_info) {
-		const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
-		vr_config = conf->vr_config;
-	}
+	/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
+	const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info;
+	vr_config = conf->vr_config;
 
 	printk(BIOS_DEBUG, "Initializing VR config.\n");
 
@@ -448,18 +446,12 @@ static void configure_c_states(void)
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }
 
-static void configure_thermal_target(void)
+static void configure_thermal_target(struct device *dev)
 {
-	struct cpu_intel_haswell_config *conf;
-	struct device *lapic;
+	/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
+	struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info;
 	msr_t msr;
 
-	/* Find pointer to CPU configuration */
-	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	if (!lapic || !lapic->chip_info)
-		return;
-	conf = lapic->chip_info;
-
 	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
@@ -551,7 +543,7 @@ static void cpu_core_init(struct device *cpu)
 	configure_misc();
 
 	/* Thermal throttle activation offset */
-	configure_thermal_target();
+	configure_thermal_target(cpu);
 
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
@@ -638,6 +630,7 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
+	cpu_cluster = cpu_bus->dev;
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(cpu_bus, &mp_ops);
 }