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-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc60
-rw-r--r--src/cpu/intel/car/romstage.c29
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc60
3 files changed, 105 insertions, 44 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 210d3566c7..d8a4fd9a83 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -337,10 +337,9 @@ before_romstage:
post_code(0x2f)
/* Call romstage.c main function. */
call romstage_main
-
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down.
- */
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -378,27 +377,48 @@ before_romstage:
post_code(0x38)
- /* Enable Write Back and Speculative Reads for low RAM. */
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
- movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRR_PHYS_MASK(0), %ecx
- rdmsr
- movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
- wrmsr
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
-#if CACHE_ROM_SIZE
- /* Enable caching and Speculative Reads for Flash ROM device. */
- movl $MTRR_PHYS_BASE(1), %ecx
- movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
wrmsr
- movl $MTRR_PHYS_MASK(1), %ecx
- rdmsr
- movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
wrmsr
-#endif
+ inc %ecx
+
+ dec %ebx
+ jmp 2b
+2:
post_code(0x39)
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 4f600342ec..14f841c08b 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -14,6 +14,7 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
+#include <cpu/x86/mtrr.h>
#include <program_loading.h>
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
@@ -41,10 +42,7 @@ void * asmlinkage romstage_main(unsigned long bist)
}
/* Get the stack to use after cache-as-ram is torn down. */
- if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
- romstage_stack_after_car = (void*)CONFIG_RAMTOP;
- else
- romstage_stack_after_car = setup_stack_and_mtrrs();
+ romstage_stack_after_car = setup_stack_and_mtrrs();
return romstage_stack_after_car;
}
@@ -54,3 +52,26 @@ void asmlinkage romstage_after_car(void)
/* Load the ramstage. */
run_ramstage();
}
+
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use. */
+void *setup_stack_and_mtrrs(void)
+{
+ struct postcar_frame pcf;
+
+ postcar_frame_init_lowmem(&pcf);
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs.
+ */
+ return postcar_commit_mtrrs(&pcf);
+}
+#endif /* CONFIG_LATE_CBMEM_INIT */
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 1673242884..21f63ecae5 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -138,10 +138,9 @@ before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
-
/* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down.
- */
+ * after cache-as-ram is torn down. It also contains the information
+ * for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -179,27 +178,48 @@ before_romstage:
post_code(0x38)
- /* Enable Write Back and Speculative Reads for low RAM. */
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
- movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
wrmsr
- movl $MTRR_PHYS_MASK(0), %ecx
- movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
wrmsr
+ inc %ecx
-#if CACHE_ROM_SIZE
- /* Enable caching and Speculative Reads for Flash ROM device. */
- movl $MTRR_PHYS_BASE(1), %ecx
- movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRR_PHYS_MASK(1), %ecx
- movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
+ dec %ebx
+ jmp 2b
+2:
post_code(0x39)