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-rw-r--r--src/cpu/intel/model_106cx/Config.lb14
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc165
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram_disable.c116
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram_post.c125
-rw-r--r--src/cpu/intel/model_106cx/model_6cx_init.c226
-rw-r--r--src/cpu/intel/socket_441/Config.lb3
-rw-r--r--src/cpu/intel/socket_441/chip.h4
-rw-r--r--src/cpu/intel/socket_441/socket_441.c7
8 files changed, 660 insertions, 0 deletions
diff --git a/src/cpu/intel/model_106cx/Config.lb b/src/cpu/intel/model_106cx/Config.lb
new file mode 100644
index 0000000000..aa1ca190f1
--- /dev/null
+++ b/src/cpu/intel/model_106cx/Config.lb
@@ -0,0 +1,14 @@
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
+
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/x86/smm
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+dir /cpu/intel/speedstep
+driver model_6cx_init.o
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
new file mode 100644
index 0000000000..92cf92f0f0
--- /dev/null
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+#define post_code(x) intel_chip_post_macro(x)
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+
+ /* Save the BIST result */
+ movl %eax, %ebp
+
+cache_as_ram:
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+
+ post_code(0x20)
+
+ /* Send INIT IPI to all excluding ourself */
+ movl $0x000C4500, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ post_code(0x21)
+
+ /* Zero out all Fixed Range and Variable Range MTRRs */
+ movl $mtrr_table, %esi
+ movl $( (mtrr_table_end - mtrr_table) / 2), %edi
+ xorl %eax, %eax
+ xorl %edx, %edx
+clear_mtrrs:
+ movw (%esi), %bx
+ movzx %bx, %ecx
+ wrmsr
+ add $2, %esi
+ dec %edi
+ jnz clear_mtrrs
+ post_code(0x22)
+
+ /* Configure the default memory type to uncacheable */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~0x00000cff), %eax
+ wrmsr
+
+ post_code(0x23)
+ /* Set cache as ram base address */
+ movl $(MTRRphysBase_MSR(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(0x24)
+ /* Set cache as ram mask */
+ movl $(MTRRphysMask_MSR(0)), %ecx
+ movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+ movl $0x00000000, %edx
+ wrmsr
+
+ post_code(0x25)
+ /* Enable MTRR */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $(1 << 11), %eax
+ wrmsr
+
+ post_code(0x26)
+ /* Enable L2 Cache */
+ movl $0x11e, %ecx
+ rdmsr
+ orl $(1 << 8), %eax
+ wrmsr
+
+ post_code(0x27)
+ /* CR0.CD = 0, CR0.NW = 0 */
+ movl %cr0, %eax
+ andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
+ invd
+ movl %eax, %cr0
+
+ post_code(0x28)
+ /* Clear the cache memory reagion */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ //movl $0x23322332, %eax
+ xorl %eax, %eax
+ rep stosl
+#endif
+
+ post_code(0x29)
+ /* Enable Cache As RAM mode by disabling cache */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
+
+#if 0
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+ /* Enable cache for our code in Flash because we do CONFIG_XIP here */
+ movl $MTRRphysBase_MSR(1), %ecx
+ xorl %edx, %edx
+ movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ wrmsr
+
+ movl $MTRRphysMask_MSR(1), %ecx
+ movl $0x0000000f, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ wrmsr
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif
+
+ post_code(0x2a)
+ /* enable cache */
+ movl %cr0, %eax
+ andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
+ movl %eax, %cr0
+
+ /* Set up stack pointer */
+ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+ movl %eax, %esp
+
+ /* Restore the BIST result */
+ movl %ebp, %eax
+ movl %esp, %ebp
+ pushl %eax
+
+ post_code(0x23)
+
+ call stage1_main
+
+ post_code(0x2f)
+error:
+ hlt
+ jmp error
+
+mtrr_table:
+ /* Fixed MTRRs */
+ .word 0x250, 0x258, 0x259
+ .word 0x268, 0x269, 0x26A
+ .word 0x26B, 0x26C, 0x26D
+ .word 0x26E, 0x26F
+ /* Variable MTRRs */
+ .word 0x200, 0x201, 0x202, 0x203
+ .word 0x204, 0x205, 0x206, 0x207
+ .word 0x208, 0x209, 0x20A, 0x20B
+ .word 0x20C, 0x20D, 0x20E, 0x20F
+mtrr_table_end:
+
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_disable.c b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
new file mode 100644
index 0000000000..a56d7b0c0f
--- /dev/null
+++ b/src/cpu/intel/model_106cx/cache_as_ram_disable.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "cpu/x86/car/copy_and_run.c"
+
+void real_main(unsigned long bist);
+
+void stage1_main(unsigned long bist)
+{
+ unsigned int cpu_reset = 0;
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ } else {
+ /* This is the primary cpu how should I boot? */
+ check_cmos_failed();
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ }
+ normal_image:
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ );
+ fallback_image:
+#endif
+
+ real_main(bist);
+
+ /* No servicable parts below this line .. */
+
+ {
+ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ "movl %%esp, %0\n\t"
+ : "=a" (v_esp)
+ );
+ printk_spew("v_esp=%08x\r\n", v_esp);
+ }
+
+cpu_reset_x:
+
+ printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+
+ if(cpu_reset == 0) {
+ print_spew("Clearing initial memory region: ");
+ }
+ print_spew("No cache as ram now - ");
+
+ /* store cpu_reset to ebx */
+ __asm__ volatile (
+ "movl %0, %%ebx\n\t"
+ ::"a" (cpu_reset)
+ );
+
+ if(cpu_reset==0) {
+#define CLEAR_FIRST_1M_RAM 1
+#include "cache_as_ram_post.c"
+ } else {
+#undef CLEAR_FIRST_1M_RAM
+#include "cache_as_ram_post.c"
+ }
+
+ __asm__ volatile (
+ /* set new esp */ /* before _RAMBASE */
+ "subl %0, %%ebp\n\t"
+ "subl %0, %%esp\n\t"
+ ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
+ );
+
+ {
+ unsigned new_cpu_reset;
+
+ /* get back cpu_reset from ebx */
+ __asm__ volatile (
+ "movl %%ebx, %0\n\t"
+ :"=a" (new_cpu_reset)
+ );
+
+#ifdef CONFIG_DEACTIVATE_CAR
+ print_debug("Deactivating CAR");
+#include CONFIG_DEACTIVATE_CAR_FILE
+ print_debug(" - Done.\r\n");
+#endif
+ /* Copy and execute coreboot_ram */
+ copy_and_run(new_cpu_reset);
+ /* We will not return */
+ }
+
+ print_debug("sorry. parachute did not open.\r\n");
+}
diff --git a/src/cpu/intel/model_106cx/cache_as_ram_post.c b/src/cpu/intel/model_106cx/cache_as_ram_post.c
new file mode 100644
index 0000000000..fd4eb34ef9
--- /dev/null
+++ b/src/cpu/intel/model_106cx/cache_as_ram_post.c
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+ __asm__ volatile (
+
+ "movb $0x30, %al\noutb %al, $0x80\n"
+
+ /* Disable Cache */
+ "movl %cr0, %eax\n"
+ "orl $(1 << 30), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x31, %al\noutb %al, $0x80\n"
+
+ /* Disable MTRR */
+ "movl $MTRRdefType_MSR, %ecx\n"
+ "rdmsr\n"
+ "andl $(~(1 << 11)), %eax\n"
+ "wrmsr\n"
+
+ "movb $0x32, %al\noutb %al, $0x80\n"
+
+ "invd\n"
+#if 0
+ "xorl %eax, %eax\n"
+ "xorl %edx, %edx\n"
+ "movl $MTRRphysBase_MSR(0), %ecx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(0), %ecx\n"
+ "wrmsr\n"
+ "movl $MTRRphysBase_MSR(1), %ecx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(1), %ecx\n"
+ "wrmsr\n"
+#endif
+
+ "movb $0x33, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+ "movb $0x34, %al\noutb %al, $0x80\n"
+ /* Enable Write Combining and Speculative Reads for the first 1MB */
+ "movl $MTRRphysBase_MSR(0), %ecx\n"
+ "movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n"
+ "xorl %edx, %edx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(0), %ecx\n"
+ "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
+ "movl $0x0000000f, %edx\n" // 36bit address space
+ "wrmsr\n"
+ "movb $0x35, %al\noutb %al, $0x80\n"
+#endif
+
+ /* Enable Cache */
+ "movl %cr0, %eax\n"
+ "andl $~( (1 << 30) | (1 << 29) ), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x36, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+
+ /* Clear first 1MB of RAM */
+ "movl $0x00000000, %edi\n"
+ "cld\n"
+ "xorl %eax, %eax\n"
+ "movl $((1024*1024) / 4), %ecx\n"
+ "rep stosl\n"
+
+ "movb $0x37, %al\noutb %al, $0x80\n"
+#endif
+
+ /* Disable Cache */
+ "movl %cr0, %eax\n"
+ "orl $(1 << 30), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x38, %al\noutb %al, $0x80\n"
+
+ /* Enable Write Back and Speculative Reads for the first 1MB */
+ "movl $MTRRphysBase_MSR(0), %ecx\n"
+ "movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax\n"
+ "xorl %edx, %edx\n"
+ "wrmsr\n"
+ "movl $MTRRphysMask_MSR(0), %ecx\n"
+ "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n"
+ "movl $0x0000000f, %edx\n" // 36bit address space
+ "wrmsr\n"
+
+ "movb $0x39, %al\noutb %al, $0x80\n"
+
+ /* And Enable Cache again after setting MTRRs */
+ "movl %cr0, %eax\n"
+ "andl $~( (1 << 30) | (1 << 29) ), %eax\n"
+ "movl %eax, %cr0\n"
+
+ "movb $0x3a, %al\noutb %al, $0x80\n"
+
+ /* Enable MTRR */
+ "movl $MTRRdefType_MSR, %ecx\n"
+ "rdmsr\n"
+ "orl $(1 << 11), %eax\n"
+ "wrmsr\n"
+
+ "movb $0x3b, %al\noutb %al, $0x80\n"
+
+ /* Invalidate the cache again */
+ "invd\n"
+ "movb $0x3c, %al\noutb %al, $0x80\n"
+ );
diff --git a/src/cpu/intel/model_106cx/model_6cx_init.c b/src/cpu/intel/model_106cx/model_6cx_init.c
new file mode 100644
index 0000000000..91697f88a9
--- /dev/null
+++ b/src/cpu/intel/model_106cx/model_6cx_init.c
@@ -0,0 +1,226 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <usbdebug_direct.h>
+
+static const uint32_t microcode_updates[] = {
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src)
+{
+ while (*src) *dst++ = *src++;
+}
+
+static void fill_processor_name(char *processor_name)
+{
+ struct cpuid_result regs;
+ char temp_processor_name[49];
+ char *processor_name_start;
+ unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+ int i;
+
+ for (i=0; i<3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i*4 + 0] = regs.eax;
+ name_as_ints[i*4 + 1] = regs.ebx;
+ name_as_ints[i*4 + 2] = regs.ecx;
+ name_as_ints[i*4 + 3] = regs.edx;
+ }
+
+ temp_processor_name[48] = 0;
+
+ /* Skip leading spaces */
+ processor_name_start = temp_processor_name;
+ while (*processor_name_start == ' ')
+ processor_name_start++;
+
+ memset(processor_name, 0, 49);
+ strcpy(processor_name, processor_name_start);
+}
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+ struct cpuid_result regs;
+ msr_t msr;
+
+ msr = rdmsr(IA32_FEATURE_CONTROL);
+
+ if (msr.lo & (1 << 0)) {
+ /* VMX locked. If we set it again we get an illegal
+ * instruction
+ */
+ return;
+ }
+
+ regs = cpuid(1);
+ if (regs.ecx & CPUID_VMX) {
+ msr.lo |= (1 << 2);
+ if (regs.ecx & CPUID_SMX)
+ msr.lo |= (1 << 1);
+ }
+
+ wrmsr(IA32_FEATURE_CONTROL, msr);
+
+ msr.lo |= (1 << 0); /* Set lock bit */
+
+ wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL 0xe2
+#define PMG_IO_BASE_ADDR 0xe3
+#define PMG_IO_CAPTURE_ADDR 0xe4
+#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
+#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state.
+ See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
+#define HIGHEST_CLEVEL 3
+static void configure_c_states(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+ msr.lo |= (1 << 15); // Lock configuration
+ msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
+ msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
+ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
+ // TODO Do we want Deep C4 and Dynamic L2 shrinking?
+ wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+ // set P_BLK address
+ msr = rdmsr(PMG_IO_BASE_ADDR);
+ msr.lo = (PMB0 + 4) | (PMB1 << 16);
+ wrmsr(PMG_IO_BASE_ADDR, msr);
+
+ // set C_LVL controls
+ msr = rdmsr(PMG_IO_CAPTURE_ADDR);
+ msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+ wrmsr(PMG_IO_CAPTURE_ADDR, msr);
+}
+
+#define IA32_MISC_ENABLE 0x1a0
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 3); /* TM1 enable */
+ msr.lo |= (1 << 13); /* TM2 enable */
+ msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
+
+ msr.lo |= (1 << 10); /* FERR# multiplexing */
+
+ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+
+ // TODO Do we want Deep C4 and Dynamic L2 shrinking?
+ wrmsr(IA32_MISC_ENABLE, msr);
+
+ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+#if CONFIG_USBDEBUG_DIRECT
+static unsigned ehci_debug_addr;
+#endif
+
+static void model_6ex_init(device_t cpu)
+{
+ char processor_name[49];
+
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Print processor name */
+ fill_processor_name(processor_name);
+ printk_info("CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG_DIRECT
+ // Is this caution really needed?
+ if(!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
+#endif
+
+ /* Setup MTRRs */
+ x86_setup_mtrrs(36);
+ x86_mtrr_check();
+
+#if CONFIG_USBDEBUG_DIRECT
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+ /* Enable virtualization */
+ enable_vmx();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* TODO: PIC thermal sensor control */
+
+ /* Start up my cpu siblings */
+ intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_6ex_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */
+ { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */
+ { X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
diff --git a/src/cpu/intel/socket_441/Config.lb b/src/cpu/intel/socket_441/Config.lb
new file mode 100644
index 0000000000..c43c5c7183
--- /dev/null
+++ b/src/cpu/intel/socket_441/Config.lb
@@ -0,0 +1,3 @@
+config chip.h
+object socket_441.o
+dir /cpu/intel/model_106cx
diff --git a/src/cpu/intel/socket_441/chip.h b/src/cpu/intel/socket_441/chip.h
new file mode 100644
index 0000000000..4c99ed63df
--- /dev/null
+++ b/src/cpu/intel/socket_441/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_441_ops;
+
+struct cpu_intel_socket_441_config {
+};
diff --git a/src/cpu/intel/socket_441/socket_441.c b/src/cpu/intel/socket_441/socket_441.c
new file mode 100644
index 0000000000..48c91c5882
--- /dev/null
+++ b/src/cpu/intel/socket_441/socket_441.c
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_441_ops = {
+ CHIP_NAME("Socket 441 CPU")
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 12:54:51 +0000