3 files changed, 20 insertions, 0 deletions
diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index de56a3a1e6..c4ac57ebcf 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1,5 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+romstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index a29fd2e6b6..d28d95c5c8 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -66,4 +66,12 @@ void set_energy_perf_pref(u8 pref);
  */
 void enable_energy_perf_pref(void);
 
+/*
+ * Check if Total Memory Encryption (TME) is supported by the CPU
+ *
+ * coreboot shall detect the existence of TME feature by running CPUID instruction:
+ * CPUID leaf 7/sub-leaf 0: Return Value in ECX [bit 13] = 1
+ */
+bool is_tme_supported(void);
+
 #endif
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index b24f742476..f8608ae029 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -14,6 +14,9 @@
 #define  CPUID_6_ENGERY_PERF_PREF	(1 << 10)
 #define  CPUID_6_HWP			(1 << 7)
 
+/* Structured Extended Feature Flags */
+#define CPUID_EXT_FEATURE_TME_SUPPORTED (1 << 13)
+
 void set_vmx_and_lock(void)
 {
 	set_feature_ctrl_vmx();
@@ -227,3 +230,11 @@ void set_energy_perf_pref(u8 pref)
 	msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK,
 		(uint64_t)pref << IA32_HWP_REQUEST_EPP_SHIFT);
 }
+
+bool is_tme_supported(void)
+{
+	struct cpuid_result cpuid_regs;
+
+	cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0);
+	return (cpuid_regs.ecx & CPUID_EXT_FEATURE_TME_SUPPORTED);
+}