diff options
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/bootblock.c | 3 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 555c3846b4..03a94eebd1 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -74,7 +74,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_init_lowmem(&pcf); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index a208ec9fbe..327c4a4ce9 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -62,8 +62,7 @@ static void enable_rom_caching(void) msr_t msr; disable_cache(); - set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1, - CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ |