diff options
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 3e2b3e24ac..024133b864 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -200,7 +200,7 @@ ap_init: post_code(0x27) /* Do not disable cache (so BSP can enable it). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 18160adfad..67a7408814 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -72,7 +72,7 @@ static void configure_c_states(void) msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 3); // Dynamic L2 - /* Number of supported C-States */ + /* Number of supported C-States */ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 |