diff options
Diffstat (limited to 'src/cpu/intel')
-rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 7 | ||||
-rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 17 | ||||
-rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 15 | ||||
-rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 15 | ||||
-rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 15 | ||||
-rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 15 |
6 files changed, 45 insertions, 39 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7742a68225..6e642f68f9 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -23,6 +23,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> @@ -254,7 +255,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -328,7 +329,7 @@ lout: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Clear sth. */ @@ -353,7 +354,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ca107c4c56..4e0f391d33 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -22,6 +22,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cpu/x86/lapic_def.h> @@ -188,7 +189,7 @@ ap_init: /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x28) @@ -271,7 +272,7 @@ no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -284,7 +285,7 @@ no_msr_11e: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x2d) @@ -310,7 +311,7 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x2e) @@ -338,7 +339,7 @@ no_msr_11e: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x34) @@ -357,14 +358,14 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x37) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -393,7 +394,7 @@ no_msr_11e: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03299..e74e24c0bd 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 32 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -207,7 +208,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index c4d3701c48..7d402e4d4e 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cbmem.h> @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -126,7 +127,7 @@ clear_mtrrs: post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ @@ -162,7 +163,7 @@ clear_mtrrs: post_code(0x28) /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer below MRC variable space. */ @@ -195,7 +196,7 @@ before_romstage: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -235,14 +236,14 @@ before_romstage: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -275,7 +276,7 @@ before_romstage: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b1138d..92337c8158 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +218,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de28a1..61feb1d8b5 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -91,7 +92,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -105,7 +106,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -129,7 +130,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -157,7 +158,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -188,14 +189,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -214,7 +215,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) |