aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/model_1067x/model_1067x_init.c1
-rw-r--r--src/cpu/intel/speedstep/acpi.c2
2 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index e81a6a7291..c821474446 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -99,7 +99,6 @@ static void enable_vmx(void)
}
#define MSR_BBL_CR_CTL3 0x11e
-#define MSR_FSB_FREQ 0xcd
static void configure_c_states(const int quad)
{
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 910055d443..dfcc82e2da 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -67,7 +67,7 @@ static int determine_total_number_of_cores(void)
*/
static int get_fsb(void)
{
- const u32 fsbcode = rdmsr(0xcd).lo & 7;
+ const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
switch (fsbcode) {
case 0: return 800; /* / 3 == 266 */
case 1: return 400; /* / 3 == 133 */