diff options
Diffstat (limited to 'src/cpu/intel/smm/gen1/smmrelocate.c')
| -rw-r--r-- | src/cpu/intel/smm/gen1/smmrelocate.c | 19 |
1 files changed, 7 insertions, 12 deletions
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 06b140ea0e..7e7f986ccf 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -114,22 +114,17 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) static void fill_in_relocation_params(struct smm_relocation_params *params) { - u32 tseg_size; - u32 tsegmb; - int phys_bits; /* All range registers are aligned to 4KiB */ const u32 rmask = ~((1 << 12) - 1); - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - northbridge_get_tseg_base_and_size(&tsegmb, &tseg_size); + const u32 tsegmb = northbridge_get_tseg_base(); + /* TSEG base is usually aligned down (to 8MiB). So we can't + derive the TSEG size from the distance to GTT but use the + configuration value instead. */ + const u32 tseg_size = CONFIG_SMM_TSEG_SIZE; + /* The SMRAM available to the handler is 4MiB + since the IEDRAM lives at TSEGMB + 4MiB. */ params->smram_base = tsegmb; params->smram_size = 4 << 20; params->ied_base = tsegmb + params->smram_size; |