diff options
Diffstat (limited to 'src/cpu/intel/model_f4x')
| -rw-r--r-- | src/cpu/intel/model_f4x/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_f4x/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_f4x/microcode_blob.c | 24 | ||||
| -rw-r--r-- | src/cpu/intel/model_f4x/model_f4x_init.c | 27 |
4 files changed, 28 insertions, 26 deletions
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 97c909a0ae..c21a2743bf 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_MODEL_F4X bool select SMP + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index ac99095b53..6ade9f3749 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1 +1,3 @@ ramstage-y += model_f4x_init.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c new file mode 100644 index 0000000000..4f1147cc50 --- /dev/null +++ b/src/cpu/intel/model_f4x/microcode_blob.c @@ -0,0 +1,24 @@ +unsigned microcode_updates_f4x[] = { + /* WARNING - Intel has a new data structure that has variable length + * microcode update lengths. They are encoded in int 8 and 9. A + * dummy header of nulls must terminate the list. + */ + + #include "microcode-1735-m01f480c.h" + #include "microcode-1460-m9df4305.h" + #include "microcode-2492-m02f480e.h" + #include "microcode-1470-m9df4703.h" + #include "microcode-1521-m5ff4807.h" + #include "microcode-1466-m02f4116.h" + #include "microcode-1469-m9df4406.h" + #include "microcode-1471-mbdf4117.h" + #include "microcode-1637-m5cf4a04.h" + #include "microcode-1462-mbdf4903.h" + #include "microcode-1498-m5df4a02.h" + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index f3f0b2af0f..80d7dc8056 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -10,31 +10,6 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static uint32_t microcode_updates[] = { - /* WARNING - Intel has a new data structure that has variable length - * microcode update lengths. They are encoded in int 8 and 9. A - * dummy header of nulls must terminate the list. - */ - - #include "microcode-1735-m01f480c.h" - #include "microcode-1460-m9df4305.h" - #include "microcode-2492-m02f480e.h" - #include "microcode-1470-m9df4703.h" - #include "microcode-1521-m5ff4807.h" - #include "microcode-1466-m02f4116.h" - #include "microcode-1469-m9df4406.h" - #include "microcode-1471-mbdf4117.h" - #include "microcode-1637-m5cf4a04.h" - #include "microcode-1462-mbdf4903.h" - #include "microcode-1498-m5df4a02.h" - - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void model_f4x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -46,7 +21,7 @@ static void model_f4x_init(device_t cpu) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); } /* Enable the local cpu apics */ |