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Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc16
1 files changed, 2 insertions, 14 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 6f13cd916d..bdefb21b59 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -83,7 +83,7 @@ clear_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -164,18 +164,6 @@ clear_mtrrs:
post_code(0x31)
invd
-#if 0
- xorl %eax, %eax
- xorl %edx, %edx
- movl $MTRRphysBase_MSR(0), %ecx
- wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
- wrmsr
- movl $MTRRphysBase_MSR(1), %ecx
- wrmsr
- movl $MTRRphysMask_MSR(1), %ecx
- wrmsr
-#endif
post_code(0x33)
@@ -193,7 +181,7 @@ clear_mtrrs:
post_code(0x38)
- /* Enable Write Back and Speculative Reads for the first 1MB. */
+ /* Enable Write Back and Speculative Reads for low RAM. */
movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx