diff options
Diffstat (limited to 'src/cpu/intel/model_6ex/model_6ex_init.c')
| -rw-r--r-- | src/cpu/intel/model_6ex/model_6ex_init.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index cc1260ea81..a93b113e0b 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -21,8 +21,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -34,10 +34,10 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset. + msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); //dynamic L2 + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -50,7 +50,7 @@ static void configure_c_states(void) msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr); - /* set C_LVL controls */ + /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); @@ -128,6 +128,9 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + /* Enable the local CPU APICs */ setup_lapic(); |