diff options
Diffstat (limited to 'src/cpu/intel/model_6ex/cache_as_ram_disable.c')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram_disable.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c index cbf7cdd37b..44ff264818 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c @@ -37,13 +37,13 @@ void stage1_main(unsigned long bist) "movl %%esp, %0\n" : "=a" (v_esp) ); - printk_spew("v_esp=%08x\n", v_esp); + printk(BIOS_SPEW, "v_esp=%08x\n", v_esp); #endif cpu_reset_x: - printk_spew("cpu_reset = %08x\n", cpu_reset); - printk_spew("No cache as ram now - "); + printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset); + printk(BIOS_SPEW, "No cache as ram now - "); /* store cpu_reset to ebx */ __asm__ volatile ( @@ -83,5 +83,5 @@ cpu_reset_x: } /* We will not return */ - printk_debug("sorry. parachute did not open.\n"); + printk(BIOS_DEBUG, "sorry. parachute did not open.\n"); } |