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path: root/src/cpu/intel/model_6ex/cache_as_ram.inc
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Diffstat (limited to 'src/cpu/intel/model_6ex/cache_as_ram.inc')
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 6b80e7ae7b..edd9e6c961 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -96,7 +96,6 @@ clear_mtrrs:
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
-#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
@@ -113,7 +112,6 @@ clear_mtrrs:
movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax