diff options
Diffstat (limited to 'src/cpu/intel/model_6ex/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b1138d..92337c8158 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +218,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) |