diff options
Diffstat (limited to 'src/cpu/intel/model_206ax')
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 6 |
2 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 98be012746..2298684421 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -12,10 +12,6 @@ void intel_model_206ax_finalize_smm(void) { - /* Lock AES-NI only if supported */ - if (cpuid_ecx(1) & (1 << 25)) - msr_set(MSR_FEATURE_CONFIG, BIT(0)); - /* Lock TM interrupts - route thermal events to all processors */ msr_set(MSR_MISC_PWR_MGMT, BIT(22)); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index cd828e8199..d23772a23f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -470,6 +470,12 @@ static void model_206ax_init(struct device *cpu) /* Thermal throttle activation offset */ configure_thermal_target(); + if (!intel_ht_sibling()) { + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) + msr_set(MSR_FEATURE_CONFIG, BIT(0)); + } + /* Enable Direct Cache Access */ configure_dca_cap(); |