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-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index fa974e53cd..60288010da 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -39,7 +39,7 @@
#include "chip.h"
/*
- * List of suported C-states in this processor
+ * List of supported C-states in this processor
*
* Latencies are typical worst-case package exit time in uS
* taken from the SandyBridge BIOS specification.
@@ -374,7 +374,7 @@ static void configure_thermal_target(void)
return;
conf = lapic->chip_info;
- /* Set TCC activaiton offset if supported */
+ /* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);