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path: root/src/cpu/intel/model_206ax/cache_as_ram.inc
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Diffstat (limited to 'src/cpu/intel/model_206ax/cache_as_ram.inc')
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 887d92bbe6..1a197071c4 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -239,7 +239,7 @@ before_romstage:
post_code(0x38)
/* Enable Write Back and Speculative Reads for the first MB
- * and coreboot_ram.
+ * and ramstage.
*/
movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax