diff options
Diffstat (limited to 'src/cpu/intel/model_2065x/cache_as_ram.inc')
-rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index cfa3b6b3bf..f36af2b3fc 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -48,8 +48,8 @@ wait_for_sipi: jc wait_for_sipi post_code(0x21) - /* Clean-up MTRRdefType_MSR. */ - movl $MTRRdefType_MSR, %ecx + /* Clean-up MTRR_DEF_TYPE_MSR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr @@ -69,7 +69,7 @@ clear_mtrrs: jnz clear_mtrrs /* Zero out all variable range MTRRs. */ - movl $MTRRcap_MSR, %ecx + movl $MTRR_CAP_MSR, %ecx rdmsr andl $0xff, %eax shl $1, %eax @@ -85,24 +85,24 @@ clear_var_mtrrs: post_code(0x23) /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx + movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr post_code(0x24) /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(MTRR_PHYS_MASK(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x25) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -139,7 +139,7 @@ clear_var_mtrrs: movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See @@ -150,9 +150,9 @@ clear_var_mtrrs: orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRR_PHYS_MASK(1), %ecx movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x27) @@ -189,9 +189,9 @@ before_romstage: post_code(0x31) /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr post_code(0x31) @@ -228,12 +228,12 @@ before_romstage: /* Enable Write Back and Speculative Reads for the first MB * and ramstage. */ - movl $MTRRphysBase_MSR(0), %ecx + movl $MTRR_PHYS_BASE(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr @@ -241,12 +241,12 @@ before_romstage: /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ - movl $MTRRphysBase_MSR(1), %ecx + movl $MTRR_PHYS_BASE(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr - movl $MTRRphysMask_MSR(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $MTRR_PHYS_MASK(1), %ecx + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr #endif @@ -261,9 +261,9 @@ before_romstage: post_code(0x3a) /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr post_code(0x3b) |