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Diffstat (limited to 'src/cpu/intel/model_106cx')
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc27
1 files changed, 0 insertions, 27 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 61f8353c0e..7fe66f9a6e 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -176,39 +176,12 @@ clear_mtrrs:
post_code(0x33)
-#undef CLEAR_FIRST_1M_RAM
-#ifdef CLEAR_FIRST_1M_RAM
- post_code(0x34)
- /* Enable Write Combining and Speculative Reads for the first 1MB */
- movl $MTRRphysBase_MSR(0), %ecx
- movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(1024*1024 -1) | (1 << 11)), %eax
- xorl %edx, %edx
- wrmsr
- post_code(0x35)
-#endif
-
/* Enable Cache */
movl %cr0, %eax
andl $~( (1 << 30) | (1 << 29) ), %eax
movl %eax, %cr0
-
post_code(0x36)
-#ifdef CLEAR_FIRST_1M_RAM
-
- /* Clear first 1MB of RAM */
- movl $0x00000000, %edi
- cld
- xorl %eax, %eax
- movl $((1024*1024) / 4), %ecx
- rep stosl
-
- post_code(0x37)
-#endif
/* Disable Cache */
movl %cr0, %eax