diff options
Diffstat (limited to 'src/cpu/intel/model_1067x/model_1067x_init.c')
| -rw-r--r-- | src/cpu/intel/model_1067x/model_1067x_init.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0d9169b757..f304b948e3 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -63,7 +63,7 @@ static void configure_c_states(const int quad) const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); if (quad) @@ -79,7 +79,7 @@ static void configure_c_states(const int quad) msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ if (c6) msr.lo |= (1 << 25); - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; @@ -129,10 +129,10 @@ static void configure_p_states(const char stepping, const char cores) wrmsr(IA32_PERF_CTL, msr); } - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 11); /* Enable hw coordination. */ msr.lo |= (1 << 15); /* Lock config until next reset. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) |