diff options
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 10 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/stage_cache.c | 30 |
3 files changed, 33 insertions, 10 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 0db047565c..57f9120d5a 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -4,9 +4,12 @@ romstage-y += romstage.c romstage-y += tsc_freq.c ramstage-y += acpi.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index b8c455bcff..8e4335f881 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <cbfs.h> -#include <cbmem.h> #include <console/console.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> @@ -313,15 +312,6 @@ void romstage_after_car(void) #if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of ram is defined to be the TSEG base address. */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); -} - void ramstage_cache_invalid(void) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c new file mode 100644 index 0000000000..162a244036 --- /dev/null +++ b/src/cpu/intel/haswell/stage_cache.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbmem.h> +#include <stage_cache.h> +#include "haswell.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of ram is defined to be the TSEG base address. */ + *size = RESERVED_SMM_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} |