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-rw-r--r--src/cpu/intel/haswell/haswell.h1
-rw-r--r--src/cpu/intel/haswell/romstage.c6
2 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 819c2e44f3..4b5a3b094a 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -141,7 +141,6 @@ struct romstage_params {
struct pei_data *pei_data;
const void *gpio_map;
const struct rcba_config_instruction *rcba_config;
- unsigned long bist;
void (*copy_spd)(struct pei_data *);
};
void romstage_common(const struct romstage_params *params);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 544a93fd97..43f5109889 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -33,14 +33,10 @@ void romstage_common(const struct romstage_params *params)
int boot_mode;
int wake_from_s3;
- if (params->bist == 0)
- enable_lapic();
+ enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
- /* Halt if there was a built in self test failure */
- report_bist_failure(params->bist);
-
/* Perform some early chipset initialization required
* before RAM initialization can work
*/