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Diffstat (limited to 'src/cpu/intel/haswell/chip.h')
| -rw-r--r-- | src/cpu/intel/haswell/chip.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 6afed37616..7c2df103a0 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,6 +3,33 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC +#include <stdbool.h> +#include <stdint.h> + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; + + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; + + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + struct cpu_intel_haswell_config { int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ @@ -13,4 +40,6 @@ struct cpu_intel_haswell_config { int c3_acpower; /* ACPI C3 on AC Power */ int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; |