diff options
Diffstat (limited to 'src/cpu/intel/haswell/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 0a070b2e81..0978bfb0ac 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -151,7 +151,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -161,7 +160,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -219,7 +217,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -227,7 +224,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33) |