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Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/core2/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/non-evict/cache_as_ram.S4
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S3
3 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index e134717b40..2e4d9c8074 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -4,6 +4,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
+#include <cpu/x86/64bit/entry64.inc>
.section .init
.global bootblock_pre_c_entry
@@ -162,8 +163,7 @@ addrsize_set_high:
subl $4, %esp
#if ENV_X86_64
-
- #include <cpu/x86/64bit/entry64.inc>
+ setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 76986ff68e..578bf03afd 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -4,6 +4,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
+#include <cpu/x86/64bit/entry64.inc>
#define NoEvictMod_MSR 0x2e0
#define BBL_CR_CTL3_MSR 0x11e
@@ -213,8 +214,7 @@ end_microcode_update:
andl $0xfffffff0, %esp
#if ENV_X86_64
-
- #include <cpu/x86/64bit/entry64.inc>
+ setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index f7c023b402..32fddd6810 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -13,6 +13,7 @@
.global bootblock_pre_c_entry
#include <cpu/intel/car/cache_as_ram_symbols.inc>
+#include <cpu/x86/64bit/entry64.inc>
.code32
_cache_as_ram_setup:
@@ -362,7 +363,7 @@ fill_cache:
subl $4, %esp
#if ENV_X86_64
- #include <cpu/x86/64bit/entry64.inc>
+ setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
movd %mm2, %rdi
shlq $32, %rdi /* BIST */