diff options
Diffstat (limited to 'src/cpu/intel/car')
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 63ee7236ea..95ecba96bd 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -315,6 +315,18 @@ no_msr_11e: orl $CR0_CacheDisable, %eax movl %eax, %cr0 + /* + * An unidentified combination of speculative reads and branch + * predictions inside WRPROT-cacheable memory can cause invalidation + * of cachelines and loss of stack on models based on NetBurst + * microarchitecture. Therefore disable WRPROT region entirely for + * all family F models. + */ + movl $1, %eax + cpuid + cmp $0xf, %ah + je skip_cache_rom + /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx @@ -332,6 +344,8 @@ no_msr_11e: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr +skip_cache_rom: + post_code(0x2e) /* Enable cache. */ movl %cr0, %eax |