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-rw-r--r--src/cpu/amd/model_10xxx/fidvid_common.c312
-rw-r--r--src/cpu/amd/model_10xxx/mc_patch_01000018.h163
-rw-r--r--src/cpu/amd/model_10xxx/mc_patch_01000033.h163
-rw-r--r--src/cpu/amd/model_10xxx/mc_patch_01000035.h163
-rw-r--r--src/cpu/amd/model_10xxx/pstate.c456
5 files changed, 1257 insertions, 0 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid_common.c b/src/cpu/amd/model_10xxx/fidvid_common.c
new file mode 100644
index 0000000000..aa82323b97
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/fidvid_common.c
@@ -0,0 +1,312 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <cpu/x86/tsc.h>
+
+
+static u32 get_vstime(u32 nodeid, u32 slam)
+{
+ u32 val;
+ u32 v;
+ device_t dev;
+
+#if defined(__ROMCC__)
+ dev = NODE_PCI(nodeid, 3);
+#else
+ dev = get_node_pci(nodeid, 3);
+#endif
+
+ val = pci_read_config32(dev, 0xd8);
+
+ val >>= slam?0:4;
+ val &= 7;
+
+ switch (val) {
+ case 4: v = 60; break;
+ case 5: v = 100; break;
+ case 6: v = 200; break;
+ case 7: v = 500; break;
+ default:
+ v = (val+1)*10; // in us
+ }
+
+ return v;
+}
+
+static void udelay_tsc(u32 us)
+{
+ /* Use TSC to delay because it is fixed, ie. it will not changed with p-states.
+ * Also, We use the APIC TIMER register is to hold flags for AP init.
+ */
+ u32 dword;
+ tsc_t tsc, tsc1, tscd;
+ u32 d = 0x00000200; //800Mhz or 200Mhz or 1.6G or get the NBFID at first
+ u32 dn = 0x1000000/2; // howmany us need to use hi
+
+ tscd.hi = us/dn;
+ tscd.lo = (us - tscd.hi * dn) * d;
+
+ tsc1 = rdtsc();
+ dword = tsc1.lo + tscd.lo;
+ if((dword<tsc1.lo) || (dword<tscd.lo)) {
+ tsc1.hi++;
+ }
+ tsc1.lo = dword;
+ tsc1.hi+= tscd.hi;
+
+ do {
+ tsc = rdtsc();
+ } while ((tsc.hi>tsc1.hi) || ((tsc.hi==tsc1.hi) && (tsc.lo>tsc1.lo)));
+
+}
+
+#ifdef __ROMCC__
+void udelay(u32 usecs)
+{
+ udelay_tsc(usecs);
+}
+#endif
+
+static u32 set_vid(u32 newvid, u32 bit_offset, u32 nodeid, u32 coreid)
+{
+ u32 val;
+ msr_t msr;
+ u32 curvid;
+ u32 slam;
+ u32 delay;
+ u32 count = 3;
+ device_t dev;
+
+ msr = rdmsr(0xc0010071);//status
+ curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits
+
+ if(newvid == curvid) return curvid;
+
+#if defined(__ROMCC__)
+ dev = NODE_PCI(nodeid, 3);
+#else
+ dev = get_node_pci(nodeid, 3);
+#endif
+
+ val = pci_read_config32(dev, 0xa0);
+
+ slam = (val >> 29) & 1;
+ delay = get_vstime(nodeid, slam);
+
+ if(!slam) {
+ if(curvid>newvid) {
+ count = (curvid - newvid) * 2;
+ } else {
+ count = (newvid - curvid) * 2;
+ }
+ }
+
+ while(count-->0) {
+ if(slam) {
+ curvid = newvid;
+ }
+ else { //ramp
+ if(curvid>newvid) {
+ curvid--;
+ } else {
+ curvid++;
+ }
+ }
+
+ msr = rdmsr(0xc0010070); //control
+ msr.lo &= ~(0x7f<<bit_offset);
+ msr.lo |= (curvid<<bit_offset);
+ wrmsr(0xc0010070, msr); // how about all copys, APIC or PCI conf space?
+
+ udelay_tsc(delay);
+
+ msr = rdmsr(0xc0010071);//status
+ curvid = (msr.lo >> bit_offset) & 0x7f; // seven bits
+
+ if(curvid == newvid) break;
+
+ }
+
+ return curvid;
+}
+
+
+static u32 set_nb_vid(u32 newvid, u32 nodeid, u32 coreid)
+{
+ return set_vid(newvid, 25, nodeid, coreid);
+}
+
+
+static u32 set_core_vid(u32 newvid, u32 nodeid, u32 coreid)
+{
+ return set_vid(newvid, 9, nodeid, coreid);
+}
+
+
+static unsigned set_cof(u32 val, u32 mask, u32 nodeid, u32 coreid)
+{
+ msr_t msr;
+ int count = 3;
+
+ val &= mask;
+
+ // FIXME: What is count for? Why 3 times? What about node and core id?
+ while(count-- > 0) {
+
+ msr = rdmsr(0xc0010071);
+ msr.lo &= mask;
+ if(msr.lo == val) break;
+
+ msr = rdmsr(0xc0010070);
+ msr.lo &= ~(mask);
+ msr.lo |= val;
+ wrmsr(0xc0010070, msr);
+ }
+
+ return msr.lo;
+}
+
+static u32 set_core_cof(u32 fid, u32 did, u32 nodeid, u32 coreid)
+{
+ u32 val;
+ u32 mask;
+
+ mask = (7<<6) | 0x3f;
+ val = ((did & 7)<<6) | (fid & 0x3f);
+
+ return set_cof(val, mask, nodeid, coreid);
+
+}
+
+
+static u32 set_nb_cof(u32 did, u32 nodeid, u32 coreid) // fid need warmreset
+{
+ u32 val;
+ u32 mask;
+
+ mask = 1<<22;
+ val = (did & 1)<<22;
+
+ return set_cof(val, mask, nodeid, coreid);
+
+}
+
+
+/* set vid and cof for core and nb after warm reset is not started by BIOS */
+static void set_core_nb_max_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // P0
+{
+ msr_t msr;
+ u32 val;
+ u32 vid;
+ u32 mask;
+ u32 did;
+ device_t dev;
+
+ msr = rdmsr(0xc0010064);
+
+#if defined(__ROMCC__)
+ dev = NODE_PCI(nodeid, 3);
+#else
+ dev = get_node_pci(nodeid, 3);
+#endif
+
+ val = pci_read_config32(dev, 0xa0);
+ if((val>>8) & 1) { // PVI
+ vid = (msr.lo >> 25) & 0x7f;
+ } else { //SVI
+ vid = (msr.lo >> 9) & 0x7f;
+ }
+ set_core_vid(vid, nodeid, coreid);
+
+ mask = (0x7<<6) | 0x3f;
+ val = msr.lo & mask;
+ set_cof(val, mask, nodeid, coreid);
+
+ //set nb cof and vid
+ did = (msr.lo >> 22) & 1;
+ vid = (msr.lo >> 25) & 0x7f;
+ if(did) {
+ set_nb_cof(did, nodeid, coreid);
+ set_nb_vid(vid, nodeid, coreid);
+ } else {
+ set_nb_vid(vid, nodeid, coreid);
+ set_nb_cof(did, nodeid, coreid);
+ }
+
+ //set the p state
+ msr.hi = 0;
+ msr.lo = 0;
+ wrmsr(0xc0010062, msr);
+
+}
+
+
+/* set vid and cof for core and nb after warm reset is not started by BIOS */
+static void set_core_nb_min_pstate_after_other_warm_reset(u32 nodeid, u32 coreid) // Px
+{
+ msr_t msr;
+ u32 val;
+ u32 vid;
+ u32 mask;
+ u32 did;
+ u32 pstate;
+ device_t dev;
+
+#if defined(__ROMCC__)
+ dev = NODE_PCI(nodeid, 3);
+#else
+ dev = get_node_pci(nodeid, 3);
+#endif
+
+
+ val = pci_read_config32(dev, 0xdc); //PstateMaxVal
+
+ pstate = (val >> 8) & 0x7;
+
+ msr = rdmsr(0xc0010064 + pstate);
+
+ mask = (7<<6) | 0x3f;
+ val = msr.lo & mask;
+ set_cof(val, mask, nodeid, coreid);
+
+ val = pci_read_config32(dev, 0xa0);
+ if((val>>8) & 1) { // PVI
+ vid = (msr.lo>>25) & 0x7f;
+ } else { //SVI
+ vid = (msr.lo>>9) & 0x7f;
+ }
+ set_core_vid(vid, nodeid, coreid);
+
+ //set nb cof and vid
+ did = (msr.lo >> 22) & 1;
+ vid = (msr.lo >> 25) & 0x7f;
+ if(did) {
+ set_nb_cof(did, nodeid, coreid);
+ set_nb_vid(vid, nodeid, coreid);
+ } else {
+ set_nb_vid(vid, nodeid, coreid);
+ set_nb_cof(did, nodeid, coreid);
+ }
+
+ //set the p state
+ msr.hi = 0;
+ msr.lo = pstate;
+ wrmsr(0xc0010062, msr);
+}
diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000018.h b/src/cpu/amd/model_10xxx/mc_patch_01000018.h
new file mode 100644
index 0000000000..eebe89b92b
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_01000018.h
@@ -0,0 +1,163 @@
+/*
+ ============================================================
+ (c) Advanced Micro Devices, Inc., 2004-2005
+
+ The enclosed microcode is intended to be used with AMD
+ Microprocessors. You may copy, view and install the
+ enclosed microcode only for development and deployment of
+ firmware, BIOS, or operating system code for computer
+ systems that contain AMD processors. You are not
+ authorized to use the enclosed microcode for any other
+ purpose.
+
+ THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
+ IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
+ WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
+ TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
+ ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume any responsibility for any errors which
+ may appear in this microcode or any other related
+ information provided to you by AMD, or result from use of
+ this microcode. AMD is not obligated to furnish, support,
+ or make any further information, software, technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The microcode is provided with "RESTRICTED RIGHTS." Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to the restrictions as set forth in FAR 52.227-14 and
+ DFAR252.227-7013, et seq., or its successor. Use of the
+ microcode by the U.S. Government constitutes
+ acknowledgement of AMD's proprietary rights in them.
+ ============================================================
+*/
+
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+
diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000033.h b/src/cpu/amd/model_10xxx/mc_patch_01000033.h
new file mode 100644
index 0000000000..d115c9f17f
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_01000033.h
@@ -0,0 +1,163 @@
+/*
+ ============================================================
+ (c) Advanced Micro Devices, Inc., 2004-2005
+
+ The enclosed microcode is intended to be used with AMD
+ Microprocessors. You may copy, view and install the
+ enclosed microcode only for development and deployment of
+ firmware, BIOS, or operating system code for computer
+ systems that contain AMD processors. You are not
+ authorized to use the enclosed microcode for any other
+ purpose.
+
+ THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
+ IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
+ WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
+ TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
+ ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume any responsibility for any errors which
+ may appear in this microcode or any other related
+ information provided to you by AMD, or result from use of
+ this microcode. AMD is not obligated to furnish, support,
+ or make any further information, software, technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The microcode is provided with "RESTRICTED RIGHTS." Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to the restrictions as set forth in FAR 52.227-14 and
+ DFAR252.227-7013, et seq., or its successor. Use of the
+ microcode by the U.S. Government constitutes
+ acknowledgement of AMD's proprietary rights in them.
+ ============================================================
+*/
+
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diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000035.h b/src/cpu/amd/model_10xxx/mc_patch_01000035.h
new file mode 100644
index 0000000000..5081bfaa0e
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_01000035.h
@@ -0,0 +1,163 @@
+/*
+ ============================================================
+ (c) Advanced Micro Devices, Inc., 2004-2005
+
+ The enclosed microcode is intended to be used with AMD
+ Microprocessors. You may copy, view and install the
+ enclosed microcode only for development and deployment of
+ firmware, BIOS, or operating system code for computer
+ systems that contain AMD processors. You are not
+ authorized to use the enclosed microcode for any other
+ purpose.
+
+ THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
+ IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
+ WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
+ TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
+ ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume any responsibility for any errors which
+ may appear in this microcode or any other related
+ information provided to you by AMD, or result from use of
+ this microcode. AMD is not obligated to furnish, support,
+ or make any further information, software, technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The microcode is provided with "RESTRICTED RIGHTS." Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to the restrictions as set forth in FAR 52.227-14 and
+ DFAR252.227-7013, et seq., or its successor. Use of the
+ microcode by the U.S. Government constitutes
+ acknowledgement of AMD's proprietary rights in them.
+ ============================================================
+*/
+
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+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
diff --git a/src/cpu/amd/model_10xxx/pstate.c b/src/cpu/amd/model_10xxx/pstate.c
new file mode 100644
index 0000000000..240f47e4b2
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/pstate.c
@@ -0,0 +1,456 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+
+#include "../../../northbridge/amd/amdfam10/amdfam10.h"
+
+#include <cpu/amd/model_10xxx_rev.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/mem.h>
+
+#include <cpu/amd/quadcore.h>
+
+#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern device_t get_node_pci(u32 nodeid, u32 fn);
+
+#include "fidvid_common.c"
+
+#define PSTATES_DEBUG 0
+
+
+
+static void inline dump_msr_pstates(u32 nodes)
+{
+#if PSTATES_DEBUG==1
+ int i, j;
+ for(j=0; j<5; j++) {
+ printk_debug("P%d:", j);
+ for(i=0;i<nodes;i++) {
+ printk_debug(" [%08x %08x] ", sysconf.msr_pstate[i*5+j].hi, sysconf.msr_pstate[i*5+j].lo);
+ }
+ printk_debug("\n");
+ }
+#endif
+}
+
+
+static void inline dump_p(const char *p_c, u32 nodes, u32 *p)
+{
+#if PSTATES_DEBUG==1
+ int i, j;
+ printk_debug(p_c);
+ printk_debug("p:");
+ for(i=0;i<nodes;i++) {
+ printk_debug(" %d ", p[i]);
+ }
+ printk_debug("\n");
+
+#endif
+}
+
+
+//according the pstate and make it work conformed to mixed conf system
+static u32 get_pwrvalue(u32 val)
+{
+ u32 times;
+ switch((val>>8)&3) {
+ case 0: times = 1000; break;
+ case 1: times = 100; break;
+ case 2: times = 10; break;
+ default:
+ //error
+ times = 1;
+ }
+
+ return (val & 0xff) * times;
+
+}
+
+
+static u32 get_powerstep(u32 val)
+{
+ u32 time;
+ if(val<4) {time = (4 - val)*100;}
+ else if(val<8) { time = (9+4-val)*10;}
+ else { time = (10+8-val) * 5; }
+
+ return time;
+
+}
+
+
+static u32 get_plllocktime(u32 val)
+{
+ u32 time;
+ switch(val) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ time = val+1; break;
+ case 4: time = 8; break;
+ case 5: time = 16; break;
+ default:
+ //erro2
+ time = 1;
+ }
+ return time;
+}
+
+
+static void disable_pstate(u32 nodes, u32 *p)
+{
+ int i;
+
+ for(i=0;i<nodes; i++) {
+ sysconf.msr_pstate[i*5+p[i]].hi &= ~(1<<(63-32));
+ }
+}
+
+
+static void match_pstate(u32 nodes, u32 *p)
+{
+ int i;
+ u32 corecof_min, pwrvalue_max, pwrval_max;
+ u32 enable;
+ enable = (sysconf.msr_pstate[0*5+p[0]].hi >> 31);
+ if(!enable) {
+ disable_pstate(nodes, p);
+ return;
+ }
+ corecof_min = ((sysconf.msr_pstate[0*5+p[0]].lo & 0x3f) + 0x10)>>((sysconf.msr_pstate[0*5+p[0]].lo>>6) & 7);
+ pwrval_max = sysconf.msr_pstate[0*5+p[0]].hi & 0x3ff;
+ pwrvalue_max = get_pwrvalue(pwrval_max);
+
+ for(i=1; i<nodes; i++) {
+ enable = (sysconf.msr_pstate[0*5+p[i]].hi >> 31);
+ if(!enable) {
+ disable_pstate(nodes, p);
+ return;
+ }
+
+ u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7);
+ u32 corecof = ((sysconf.msr_pstate[i*5+p[i]].lo & 0x3f) + 0x10)>>coredid;
+ if(corecof<corecof_min) corecof_min = corecof;
+ u32 pwrval, pwrvalue;
+ pwrval = sysconf.msr_pstate[i*5+p[i]].hi & 0x3ff;
+ pwrvalue = get_pwrvalue(pwrval);
+ if(pwrvalue>pwrvalue_max) {
+ pwrvalue_max = pwrvalue;
+ pwrval_max = pwrval;
+ }
+ }
+
+ for(i=0; i<nodes; i++) {
+ u32 coredid = ((sysconf.msr_pstate[i*5+p[i]].lo>>6) & 7);
+ u32 corefid = (corecof_min<<coredid);
+ while(corefid<0x10) {
+ coredid++;
+ corefid = (corecof_min<<coredid);
+ }
+ sysconf.msr_pstate[i*5+p[i]].lo &= ~(0x1ff);
+ sysconf.msr_pstate[i*5+p[i]].lo |= (corefid - 0x10) | (coredid << 6);
+ sysconf.msr_pstate[i*5+p[i]].hi &= ~(0x3ff);
+ sysconf.msr_pstate[i*5+p[i]].hi |= pwrval_max;
+ }
+}
+
+
+static void match_pstates(u32 nodes, u32 *p, u32 *px)
+{
+ int i;
+ int j;
+ u32 p_int[NODE_NUMS];
+
+ int jj=1;
+ u32 end = 0;
+ for(i=0;i<nodes; i++) {
+ p_int[i] = px[i];
+ }
+ while(1){
+ for(i=0;i<nodes; i++) {
+ if(px[i]<=(p[i]+jj)) {
+ end = 1;
+ break;
+ }
+ }
+ if(!end) {
+ for(i=0; i<nodes; i++) {
+ p_int[i] = px[i] - jj;
+ }
+ match_pstate(nodes, p_int);
+ dump_p("P int\n", nodes, p_int);
+ jj++;
+ }
+ else {
+ for(i=0;i<nodes; i++) {
+ for(j=p[i]+1; j<p_int[i]; j++) {
+ sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32));
+ }
+ }
+ break;
+ }
+ }
+}
+
+
+void prep_pstates_all(void)
+{
+ device_t f3_dev[NODE_NUMS], f4_dev[NODE_NUMS];
+ u32 p[NODE_NUMS];
+ u32 p_htc[NODE_NUMS];
+ u32 p_lowest[NODE_NUMS];
+ u32 htc_cap = 1;
+ u32 lowest_htc_equal = 0;
+
+ u32 nodes = sysconf.nodes;
+ int i;
+ int j;
+ u32 val;
+ u32 nbdid;
+ u32 nbvid0;
+ u32 nbvid1;
+
+ for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage...
+ f3_dev[i] = get_node_pci(i, 3);
+ f4_dev[i] = get_node_pci(i, 4);
+ }
+
+ for(i=0;i<nodes; i++) { // get the value from F4x1F0:E0 or we can get that msr in CAR stage...
+ val = pci_read_config32(f4_dev[i], 0x1f4);
+ nbvid0 = val & 0x3f;
+ nbvid1 = (val>>7) & 0x3f;
+ for(j=0; j<5; j++) {
+ val = pci_read_config32(f4_dev[i], 0x1e0 + (j<<2));
+ nbdid = ((val>>16) & 1);
+ sysconf.msr_pstate[i*5+j].lo = (val & 0xffff) | (nbdid<<22) | ((nbdid?nbvid1:nbvid0)<<25);
+ sysconf.msr_pstate[i*5+j].hi = (((val>>17) & 0x3ff) << (32-32)) | (((val>>27) & 1)<<(63-32));
+ }
+ }
+
+ dump_msr_pstates(nodes);
+
+ sysconf.needs_update_pstate_msrs = 0; // normal case for all sockets are installed same conf CPU
+
+ for(i=1; (i<nodes) && (!sysconf.needs_update_pstate_msrs); i++) {
+ for(j=0; j<5; j++) {
+ if((sysconf.msr_pstate[i*5+j].lo != sysconf.msr_pstate[0*5+j].lo) || (sysconf.msr_pstate[i*5+j].hi != sysconf.msr_pstate[0*5+j].hi)) {
+ sysconf.needs_update_pstate_msrs = 1;
+ break;
+ }
+ }
+ }
+
+ if(sysconf.needs_update_pstate_msrs) {
+
+ // update msr_pstate for mixed conf
+
+ //P0
+ /* Match P0 cpu cof for all cpu cores to the lowest P0 cpu cof value in the coherent fabric, and match P0 power for all cpu cores to the highest P0 power value */
+ for(i=0;i<nodes; i++) p[i] = 0;
+ match_pstate(nodes, p);
+ dump_p("P0\n", nodes, p);
+ dump_msr_pstates(nodes);
+
+
+ //p_htc
+ for(i=0;i<nodes; i++) {
+ val = pci_read_config32(f3_dev[i], 0xe8); //htc cap
+ if(!(val & (1<<10))) {
+ htc_cap = 0;
+ break;
+ }
+
+ //HtcPstateLimit
+ val = pci_read_config32(f3_dev[i], 0x64);
+ p_htc[i] = (((val>>28) & 7));
+ if(p_htc[i] == 0) {
+ val |= 1<<28;
+ pci_write_config32(f3_dev[i], 0x64, val);
+ val = pci_read_config32(f3_dev[i], 0x68); //stc
+ val &= ~(7<<28);
+ val |= (1<<28);
+ pci_write_config32(f3_dev[i], 0x68, val);
+
+ p_htc[i] = 1;
+ }
+ }
+ if(htc_cap) {
+ match_pstate(nodes, p_htc);
+
+ dump_p("P_htc\n", nodes, p_htc);
+ dump_msr_pstates(nodes);
+ }
+
+ //p_lowest
+ for(i=0;i<nodes; i++) {
+ p_lowest[i] = 0;
+ for(j=1; j<5; j++) {
+ if(sysconf.msr_pstate[i*5+j].hi & (1<<(63-32))) {
+ p_lowest[i] = j;
+ }
+ }
+ // PstateMaxVal
+ val = pci_read_config32(f3_dev[i], 0xdc);
+ if(p_lowest[i]>((val>>8) & 7)) {
+ val &= ~(7<<8);
+ val |= (p_lowest[i])<<8;
+ pci_write_config32(f3_dev[i], 0xdc, val);
+ }
+ else {
+ p_lowest[i] = (val>>8) & 7;
+ }
+ }
+ if(htc_cap) {
+ for(i=0;i<nodes; i++) {
+ if(p_lowest[i]==p_htc[i]){
+ lowest_htc_equal = 1;
+ break;
+ }
+ }
+ }
+ if(lowest_htc_equal) {
+ for(i=0;i<nodes; i++) {
+ // PstateMaxVal
+ val = pci_read_config32(f3_dev[i], 0xdc);
+ val &= ~(7<<8);
+ val |= p_htc[i];
+ pci_write_config32(f3_dev[i], 0xdc, val);
+ for(j=p_htc[i]+1; j<5; j++) {
+ sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32));
+ }
+ }
+ } else {
+ match_pstate(nodes, p_lowest);
+ for(i=0; i<nodes; i++) {
+ for(j=p_lowest[i]+1; j<5; j++) {
+ sysconf.msr_pstate[i*5+j].hi &= ~(1<<(63-32));
+ }
+ }
+
+ }
+
+ dump_p("Px\n", nodes, p_lowest);
+ dump_msr_pstates(nodes);
+
+
+ if(htc_cap) {
+ //p_up_int
+ match_pstates(nodes, p, p_htc);
+
+ dump_msr_pstates(nodes);
+
+ //p_lower_int
+ match_pstates(nodes, p_htc, p_lowest);
+ } else {
+ match_pstates(nodes, p, p_lowest);
+ }
+
+ dump_msr_pstates(nodes);
+
+ }
+
+ // fill data into p_state
+ for(i=0; i<nodes; i++) {
+ sysconf.p_state_num = 0;
+ u32 corefid_equal = 1;
+ u32 corefid;
+ corefid = (sysconf.msr_pstate[i*5+0].lo & 0x3f);
+ for(j=1; j<5; j++) {
+ msr_t *msr_pstate;
+ msr_pstate = &(sysconf.msr_pstate[i*5+j]);
+ if(!(msr_pstate->hi & (1<<(63-32)) )) continue;
+ if((msr_pstate->lo & 0x3f) != corefid) {
+ corefid_equal = 0;
+ break;
+ }
+ }
+ for(j=0; j<5; j++) {
+ struct p_state_t *p_state;
+ msr_t *msr_pstate;
+ msr_pstate = &sysconf.msr_pstate[i*5+j];
+ if(!(msr_pstate->hi & (1<<(63-32)) )) continue;
+ p_state = &sysconf.p_state[i*5+sysconf.p_state_num];
+ u32 coredid = ((msr_pstate->lo>>6) & 7);
+ u32 corecof = ((msr_pstate->lo & 0x3f) + 0x10)>>coredid;
+ p_state->corefreq = corecof;
+
+ u32 pwrval, pwrvalue;
+ pwrval = msr_pstate->hi & 0x3ff;
+ pwrvalue = get_pwrvalue(pwrval);
+ p_state->power = pwrvalue;
+
+ u32 lat;
+ val = pci_read_config32(f3_dev[i], 0xd4);
+ lat = 15 * (get_powerstep((val>>24)& 0xf)+get_powerstep((val>>20)& 0xf)) /1000;
+ if(!corefid_equal) {
+ val = pci_read_config32(f3_dev[i], 0xa0);
+ lat += get_plllocktime((val >> 11 ) & 7);
+ }
+ p_state->transition_lat = lat;
+ p_state->busmaster_lat = lat;
+
+ p_state->control = j;
+ p_state->status = j;
+
+ sysconf.p_state_num++;
+ }
+ // don't need look at other nodes
+ if(!sysconf.p_state_num) break;
+ }
+}
+
+
+//it will update pstates info from ram into MSR
+void init_pstates(device_t dev, u32 nodeid, u32 coreid)
+{
+ int j;
+ msr_t msr;
+
+ if(sysconf.needs_update_pstate_msrs) {
+ for(j=0; j < 5; j++) {
+ wrmsr(0xC0010064 + j, sysconf.msr_pstate[nodeid * 5 + j]);
+ }
+ }
+
+ /* Set TSC Freq Select: TSC increments at the rate of the core P-state 0 */
+ msr = rdmsr(0xC0010015);
+ msr.lo |= 1 << 24;
+ wrmsr(0xC0010015, msr);
+
+ // Enter the state P0
+ //FIXME I don't think that this works correctly. May depend on early fid/vid setup.
+ if(sysconf.p_state_num)
+ set_core_nb_max_pstate_after_other_warm_reset(nodeid, coreid);
+
+}
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