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-rw-r--r--src/cpu/amd/agesa/Kconfig2
-rw-r--r--src/cpu/amd/agesa/Makefile.inc1
-rw-r--r--src/cpu/amd/agesa/family12/Kconfig24
-rw-r--r--src/cpu/amd/agesa/family12/Makefile.inc43
-rw-r--r--src/cpu/amd/agesa/family12/chip_name.c18
-rw-r--r--src/cpu/amd/agesa/family12/fixme.c103
-rw-r--r--src/cpu/amd/agesa/family12/model_12_init.c106
-rw-r--r--src/cpu/amd/agesa/family12/romstage.c27
8 files changed, 0 insertions, 324 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index d14eb4054f..b6b757f6ae 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -13,7 +13,6 @@
config CPU_AMD_AGESA
bool
- default y if CPU_AMD_AGESA_FAMILY12
default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB
@@ -67,7 +66,6 @@ config S3_DATA_SIZE
endif # CPU_AMD_AGESA
-source src/cpu/amd/agesa/family12/Kconfig
source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15tn/Kconfig
source src/cpu/amd/agesa/family16kb/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index d99f2b051f..4a23ac4838 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -10,7 +10,6 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
deleted file mode 100644
index 0324d129a3..0000000000
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-config CPU_AMD_AGESA_FAMILY12
- bool
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY12
-
-config CPU_ADDR_BITS
- int
- default 48
-
-endif
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
deleted file mode 100644
index 1a7465d81f..0000000000
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ /dev/null
@@ -1,43 +0,0 @@
-#*****************************************************************************
-#
-# Copyright (c) 2011, Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-# * Redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer.
-# * Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-# * Neither the name of Advanced Micro Devices, Inc. nor the names of
-# its contributors may be used to endorse or promote products derived
-# from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#*****************************************************************************
-
-romstage-y += fixme.c
-romstage-y += romstage.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_12_init.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c
deleted file mode 100644
index ca3c39e0ab..0000000000
--- a/src/cpu/amd/agesa/family12/chip_name.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_family12_ops = {
- CHIP_NAME("AMD CPU Family 12h")
-};
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
deleted file mode 100644
index c1d4c7d1a6..0000000000
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /* Enable MMIO on AMD CPU Address Map Controller */
-
- /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
- PciData = 0x00000B00;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
- PciData = 0x00000A03;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Set TOM-DFFFFFFF to Node0 Link0. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
- PciData = 0x00DFFF00;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
- PciData = (UINT32) MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC);
- PciData = 0x00FFFF00 | 0x80;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);
- PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
-//- PciData = 0x0000F000;
- PciData = 0x00FFF000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
- PciData = 0x00000013;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
-
-void amd_initmmio(void)
-{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
- Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
- LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
- /* Enable Non-Post Memory in CPU */
- PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
- PciData = (PciData >> 8) & ~0xff;
- PciData |= 0x80;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Enable memory access */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
- LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
- PciData |= BIT1;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
- LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
-
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
deleted file mode 100644
index c0669a857d..0000000000
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/multicore.h>
-
-static void model_12_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Model 12 Init.\n");
-
- u8 i;
- msr_t msr;
- int num_banks;
-
-#if CONFIG(LOGICAL_CPUS)
- u32 siblings;
-#endif
-
-// struct node_core_id id;
-// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
-// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
-
- /* Turn on caching if we haven't already */
- x86_enable_cache();
- amd_setup_mtrrs();
- x86_mtrr_check();
-
- disable_cache();
-
- /* zero the machine check error status registers */
- msr = rdmsr(IA32_MCG_CAP);
- num_banks = msr.lo & MCA_BANKS_MASK;
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-
- enable_cache();
-
- /* Enable the local CPU APICs */
- setup_lapic();
-
- /* Set the processor name string */
- // init_processor_name();
-
-#if CONFIG(LOGICAL_CPUS)
- siblings = cpuid_ecx(0x80000008) & 0xff;
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
- /* Write protect SMM space with SMMLOCK. */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = model_12_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
- { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
- { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
- { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
- { 0, 0 },
-};
-
-static const struct cpu_driver model_12 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
deleted file mode 100644
index bca2baf483..0000000000
--- a/src/cpu/amd/agesa/family12/romstage.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-#include "sb_cimx.h"
-#include "SbPlatform.h"
-#include "platform_cfg.h"
-
-void platform_once(struct sysinfo *cb)
-{
- gpioEarlyInit();
-
- sb_poweron_init();
-
- board_BeforeAgesa(cb);
-}
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