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-rw-r--r--src/cpu/amd/car/disable_cache_as_ram.c2
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c2
-rw-r--r--src/cpu/amd/geode_lx/msrinit.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 24533c7eb9..7776ae7224 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
wrmsr(MTRRfix4K_C0000_MSR, msr);
#endif
- /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
+ /* disable fixed mtrr from now on, it will be enabled by ramstage again*/
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index f74f915ec5..97127855be 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -153,7 +153,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
set_sysinfo_in_ram(1); // So other core0 could start to train mem
- /*copy and execute coreboot_ram */
+ /*copy and execute ramstage */
copy_and_run();
/* We will not return */
diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c
index 11182501c1..84fa548d59 100644
--- a/src/cpu/amd/geode_lx/msrinit.c
+++ b/src/cpu/amd/geode_lx/msrinit.c
@@ -42,11 +42,11 @@ static const msrinit_t msr_table[] =
/* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
* It doesn't really matter in fact how much, however, because the only usage
- * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
+ * of this extended memory will be to host the ramstage stage at RAMBASE,
* currently 1Mb.
* These registers will be set to their correct value by the Northbridge init code.
*
- * WARNING: if coreboot_ram could not be loaded, these registers are probably
+ * WARNING: if ramstage could not be loaded, these registers are probably
* incorrectly set here. You may comment the following two lines and set RAMBASE
* to 0x4000 to revert to the previous behavior for LX-boards.
*/