diff options
Diffstat (limited to 'src/cpu/amd')
28 files changed, 180 insertions, 180 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 94990a66f7..50b78d0c92 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -18,13 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CacheSize DCACHE_RAM_SIZE +#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) /* leave some space for global variable to pass to RAM stage */ -#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE +#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -/* for CAR_FAM10 */ +/* for CONFIG_CAR_FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ #define MSR_FAM10 0xC001102A @@ -72,7 +72,7 @@ cache_as_ram_setup: cvtsd2si %xmm3, %ebx /* hope we can skip the double set for normal part */ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx @@ -248,10 +248,10 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#endif /* USE_FAILOVER_IMAGE == 1*/ +#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) /* disable cache */ movl %cr0, %eax orl $(1 << 30),%eax @@ -259,25 +259,25 @@ clear_fixed_var_mtrr_out: #endif -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $0x203, %ecx - movl $0xff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for K8 (CPU_ADDR_BITS = 40) */ + movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */ jmp_if_k8(wbcache_post_fam10_setup) - movl $0xffff, %edx /* (1 << (CPU_ADDR_BITS - 32)) - 1 for FAM10 (CPU_ADDR_BITS = 48) */ + movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Set the default memory type and enable fixed and variable MTRRs */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx @@ -313,7 +313,7 @@ fam10_end_part1: movb $0xA2, %al outb %al, $0x80 -#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Read the range with lodsl*/ cld movl $CacheBase, %esi @@ -325,7 +325,7 @@ fam10_end_part1: xorl %eax, %eax rep stosl -#endif /*USE_FAILOVER_IMAGE == 1*/ +#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/ /* set up the stack pointer */ movl $(CacheBase + CacheSize - GlobalVarSize), %eax diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c index 8b97129ec6..0b50480142 100644 --- a/src/cpu/amd/car/clear_init_ram.c +++ b/src/cpu/amd/car/clear_init_ram.c @@ -7,11 +7,11 @@ static void __attribute__((noinline)) clear_init_ram(void) // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); + clear_memory( CONFIG_RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE)); #endif } diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c index 437b91d4ac..f495f6dbba 100644 --- a/src/cpu/amd/car/copy_and_run.c +++ b/src/cpu/amd/car/copy_and_run.c @@ -8,7 +8,7 @@ void cbfs_and_run_core(char*, unsigned ebp); static void copy_and_run(void) { -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_ram", 0); # else cbfs_and_run_core("normal/coreboot_ram", 0); @@ -19,7 +19,7 @@ static void copy_and_run(void) static void copy_and_run_ap_code_in_car(unsigned ret_addr) { -# if USE_FALLBACK_IMAGE == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_and_run_core("fallback/coreboot_apc", ret_addr); # else cbfs_and_run_core("normal/coreboot_apc", ret_addr); diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f5f831270..a5113474d3 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -16,7 +16,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) "xorl %edx, %edx\n\t" "xorl %eax, %eax\n\t" "wrmsr\n\t" -#if DCACHE_RAM_SIZE > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 "movl $0x268, %ecx\n\t" /* fix4k_c0000*/ "wrmsr\n\t" #endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 89366e0e33..9e988f02be 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -64,7 +64,7 @@ static void post_cache_as_ram(void) set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */ -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); /* from here don't store more data in CAR */ @@ -76,14 +76,14 @@ static void post_cache_as_ram(void) ); #endif - memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline + memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) ) ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp #if 0 __asm__ volatile ( @@ -102,18 +102,18 @@ static void post_cache_as_ram(void) disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); - clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) + clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)) print_debug("Done\r\n"); // dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00); -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif set_sysinfo_in_ram(1); // So other core0 could start to train mem -#if MEM_TRAIN_SEQ == 1 -// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); +#if CONFIG_MEM_TRAIN_SEQ == 1 +// struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 899b859d4f..8401818fb6 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -110,7 +110,7 @@ unsigned get_apicid_base(unsigned ioapic_num) if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n"); + printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n"); enable_apic_ext_id(nodes); } diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 5a61fac699..331c75909a 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -19,7 +19,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) #if SET_NB_CFG_54 == 1 static inline uint8_t set_apicid_cpuid_lo(void) { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif @@ -56,7 +56,7 @@ static inline void start_other_cores(void) unsigned nodes; unsigned nodeid; - if (HAVE_OPTION_TABLE && + if (CONFIG_HAVE_OPTION_TABLE && read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { return; // disable dual_core } @@ -70,7 +70,7 @@ static inline void start_other_cores(void) } } -#if USE_DCACHE_RAM == 0 +#if CONFIG_USE_DCACHE_RAM == 0 static void do_k8_init_and_stop_secondaries(void) { struct node_core_id id; @@ -106,22 +106,22 @@ static void do_k8_init_and_stop_secondaries(void) pci_write_config32(dev_f0, 0x68, val); /* Set the lapicid */ - #if (ENABLE_APIC_EXT_ID == 1) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) unsigned initial_apicid = get_initial_apicid(); - #if LIFT_BSP_APIC_ID == 0 + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( initial_apicid != 0 ) // other than bsp #endif { /* use initial apic id to lift it */ uint32_t dword = lapic_read(LAPIC_ID); dword &= ~(0xff<<24); - dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24); + dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); lapic_write(LAPIC_ID, dword); } - #if LIFT_BSP_APIC_ID == 1 - bsp_apicid += APIC_ID_OFFSET; + #if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif #endif diff --git a/src/cpu/amd/model_10xxx/Config.lb b/src/cpu/amd/model_10xxx/Config.lb index 47303be0e8..884f1e84f4 100644 --- a/src/cpu/amd/model_10xxx/Config.lb +++ b/src/cpu/amd/model_10xxx/Config.lb @@ -17,13 +17,13 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_INIT_TIMER -uses HAVE_MOVNTI -uses CPU_ADDR_BITS +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_HAVE_MOVNTI +uses CONFIG_CPU_ADDR_BITS -default HAVE_INIT_TIMER=1 -default HAVE_MOVNTI=1 -default CPU_ADDR_BITS=48 +default CONFIG_HAVE_INIT_TIMER=1 +default CONFIG_HAVE_MOVNTI=1 +default CONFIG_CPU_ADDR_BITS=48 dir /cpu/x86/tsc dir /cpu/x86/fpu dir /cpu/x86/mmx diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 92eb2de0c8..66959839c2 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -19,7 +19,7 @@ #include "defaults.h" -//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID +//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef FAM10_SET_FIDVID #define FAM10_SET_FIDVID 1 #endif @@ -58,13 +58,13 @@ static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); -#if PCI_IO_CFG_EXT == 1 +#if CONFIG_PCI_IO_CFG_EXT == 1 static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; msr_t msr; msr = rdmsr(NB_CFG_MSR); - // EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range + // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range msr.hi |= (1<<(46-32)); wrmsr(NB_CFG_MSR, msr); } @@ -80,12 +80,12 @@ static void set_EnableCf8ExtCfg(void) { } static void set_pci_mmio_conf_reg(void) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT msr_t msr; msr = rdmsr(0xc0010058); msr.lo &= ~(0xfff00000 | (0xf << 2)); // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space - msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0); + msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0); msr.hi &= ~(0x0000ffff); msr.hi |= (PCI_MMIO_BASE >> (32-8)); wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg @@ -168,11 +168,11 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, for (j = jstart; j <= jend; j++) { ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64); - #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0) - #if LIFT_BSP_APIC_ID == 0 + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( (i != 0) || (j != 0)) /* except bsp */ #endif - ap_apicid += APIC_ID_OFFSET; + ap_apicid += CONFIG_APIC_ID_OFFSET; #endif if(ap_apicid == bsp_apicid) continue; @@ -307,8 +307,8 @@ static void STOP_CAR_AND_CPU() } -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif #if RAMINIT_SYSINFO == 1 @@ -337,7 +337,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) if(id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ set_EnableCf8ExtCfg(); /* only set it on core0 */ - #if (ENABLE_APIC_EXT_ID == 1) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) enable_apic_ext_id(id.nodeid); #endif } @@ -345,23 +345,23 @@ static u32 init_cpus(u32 cpu_init_detectedx) enable_lapic(); -#if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0) +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); - #if LIFT_BSP_APIC_ID == 0 + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( initial_apicid != 0 ) // other than bsp #endif { /* use initial apic id to lift it */ u32 dword = lapic_read(LAPIC_ID); dword &= ~(0xff << 24); - dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24); + dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24); lapic_write(LAPIC_ID, dword); } - #if LIFT_BSP_APIC_ID == 1 - bsp_apicid += APIC_ID_OFFSET; + #if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif #endif @@ -478,8 +478,8 @@ static void start_node(u8 node) /* Enable routing table */ printk_debug("Start node %02x", node); -#if CAR_FAM10 == 1 - /* For CAR_FAM10 support, we need to set Dram base/limit for the new node */ +#if CONFIG_CAR_FAM10 == 1 + /* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); #endif diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index f7f717d110..f996247d8d 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -47,7 +47,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { * 00100F62h (DA-C2) 1062h 0100009Fh */ -#include AMD_UCODE_PATCH_FILE +#include CONFIG_AMD_UCODE_PATCH_FILE #endif /* Dummy terminator */ diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb index 550716bc38..28ba85f8a9 100644 --- a/src/cpu/amd/model_fxx/Config.lb +++ b/src/cpu/amd/model_fxx/Config.lb @@ -1,10 +1,10 @@ -uses HAVE_INIT_TIMER -uses HAVE_MOVNTI -uses CPU_ADDR_BITS +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_HAVE_MOVNTI +uses CONFIG_CPU_ADDR_BITS -default HAVE_INIT_TIMER=1 -default HAVE_MOVNTI=1 -default CPU_ADDR_BITS=40 +default CONFIG_HAVE_INIT_TIMER=1 +default CONFIG_HAVE_MOVNTI=1 +default CONFIG_CPU_ADDR_BITS=40 dir /cpu/x86/tsc dir /cpu/x86/fpu dir /cpu/x86/mmx diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index f0f7b7fdd2..f079776f25 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -73,7 +73,7 @@ static void enable_fid_change(void) // dword = 0x00070000; /* enable FID/VID change */ pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword); -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME dword = 0x21132113; #else dword = 0x00132113; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 8b613a624e..435167e94a 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -1,6 +1,6 @@ -//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID +//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef K8_SET_FIDVID - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 #define K8_SET_FIDVID 0 #else // for rev F, need to set FID to max @@ -72,7 +72,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p nodes = get_nodes(); disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1 +#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core disable_siblings = 1; } @@ -87,7 +87,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3); if(nb_cfg_54) { if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -119,11 +119,11 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t p ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - #if (ENABLE_APIC_EXT_ID == 1) - #if LIFT_BSP_APIC_ID == 0 + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( (i!=0) || (j!=0)) /* except bsp */ #endif - ap_apicid += APIC_ID_OFFSET; + ap_apicid += CONFIG_APIC_ID_OFFSET; #endif if(ap_apicid == bsp_apicid) continue; @@ -238,12 +238,12 @@ static void STOP_CAR_AND_CPU(void) stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } -#ifndef MEM_TRAIN_SEQ -#define MEM_TRAIN_SEQ 0 +#ifndef CONFIG_MEM_TRAIN_SEQ +#define CONFIG_MEM_TRAIN_SEQ 0 #endif -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif @@ -268,7 +268,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */ if(id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ - #if ENABLE_APIC_EXT_ID == 1 + #if CONFIG_ENABLE_APIC_EXT_ID == 1 enable_apic_ext_id(id.nodeid); #endif } @@ -276,22 +276,22 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) enable_lapic(); // init_timer(); // We need TMICT to pass msg for FID/VID change - #if (ENABLE_APIC_EXT_ID == 1) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) unsigned initial_apicid = get_initial_apicid(); - #if LIFT_BSP_APIC_ID == 0 + #if CONFIG_LIFT_BSP_APIC_ID == 0 if( initial_apicid != 0 ) // other than bsp #endif { /* use initial apic id to lift it */ uint32_t dword = lapic_read(LAPIC_ID); dword &= ~(0xff<<24); - dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24); + dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); lapic_write(LAPIC_ID, dword); } - #if LIFT_BSP_APIC_ID == 1 - bsp_apicid += APIC_ID_OFFSET; + #if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif #endif @@ -346,7 +346,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu set_init_ram_access(); - #if MEM_TRAIN_SEQ == 1 + #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU); #endif diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 3bccfe0d83..d183bf89bc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -32,15 +32,15 @@ void cpus_ready_for_init(void) { -#if MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); +#if CONFIG_MEM_TRAIN_SEQ == 1 + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif } -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid) } #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; @@ -289,8 +289,8 @@ static void init_ecc_memory(unsigned node_id) startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2; endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; -#if HW_MEM_HOLE_SIZEK != 0 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { #endif @@ -300,7 +300,7 @@ static void init_ecc_memory(unsigned node_id) if(val & 1) { hole_startk = ((val & (0xff<<24)) >> 10); } - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 } #endif #endif @@ -322,7 +322,7 @@ static void init_ecc_memory(unsigned node_id) disable_lapic(); /* Walk through 2M chunks and zero them */ -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */ if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) { for(basek = begink; basek < hole_startk; @@ -368,7 +368,7 @@ static void init_ecc_memory(unsigned node_id) static inline void k8_errata(void) { msr_t msr; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Erratum 63... */ msr = rdmsr(HWCR_MSR); @@ -438,7 +438,7 @@ static inline void k8_errata(void) } #endif -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) #endif { @@ -453,7 +453,7 @@ static inline void k8_errata(void) msr.lo |= 1 << 6; wrmsr(HWCR_MSR, msr); -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 /* Erratum 131... */ msr = rdmsr(NB_CFG_MSR); msr.lo |= 1 << 20; @@ -478,7 +478,7 @@ void model_fxx_init(device_t dev) unsigned siblings; #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 struct cpuinfo_x86 c; get_fms(&c, dev->device); @@ -564,7 +564,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ @@ -606,7 +606,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 /* * AMD F0 support. * diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index e210846479..68a2cea070 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -52,13 +52,13 @@ $1.0$ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 #include "microcode_rev_c.h" #include "microcode_rev_d.h" #include "microcode_rev_e.h" #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 // #include "microcode_rev_f.h" #endif /* Dummy terminator */ @@ -70,7 +70,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 0x0f48, 0x0048, 0x0f58, 0x0048, @@ -93,7 +93,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { 0x20fb1, 0x0210, #endif - #if K8_REV_F_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 1 #endif diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 6ad1686dad..b68382761f 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -169,7 +169,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) cpuid1 = cpuid(0x80000001); pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14); for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++) - if (TDP[index].socket_type == CPU_SOCKET_TYPE && + if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE && TDP[index].cmp_cap == cmp_cap && TDP[index].pwr_lmt == pwr_lmt) { power_limit = TDP[index].power_limit; diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index df187cb1d2..5c87266f23 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -41,7 +41,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 static char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -163,7 +163,7 @@ int init_processor_name(void) char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -187,7 +187,7 @@ int init_processor_name(void) processor_name_string = "AMD Processor model unknown"; #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 u32 Socket; u32 CmpCap; u32 PwrLmt; @@ -343,7 +343,7 @@ int init_processor_name(void) for (i=0; i<47; i++) { // 48 -1 if(program_string[i] == program_string[i+1]) { switch (program_string[i]) { -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': @@ -352,7 +352,7 @@ int init_processor_name(void) case 'V': ModelNumber = 9 + NN; break; #endif -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 case 'R': ModelNumber = NN - 1; break; case 'P': ModelNumber = 26 + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c index dc1b680836..3c71cdb408 100644 --- a/src/cpu/amd/model_gx2/vsmsetup.c +++ b/src/cpu/amd/model_gx2/vsmsetup.c @@ -271,7 +271,7 @@ void do_vsmbios(void) //rom = 0xfff80000; //rom = 0xfffc0000; /* the VSA starts at the base of rom - 64 */ - rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); + rom = ((unsigned long) 0) - (CONFIG_ROM_SIZE + 64*1024); buf = (unsigned char *) 0x60000; olen = unrv2b((uint8_t *)rom, buf, &ilen); diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc index 57bfc1211f..c9e538ad93 100644 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ b/src/cpu/amd/model_lx/cache_as_ram.inc @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ -#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1) +#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) #define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ #define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ @@ -82,7 +82,7 @@ DCacheSetup: xorl %esi, %esi xorl %ebp, %ebp - /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */ + /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ /* remember, there is NO stack yet... */ /* Tell cache we want to fill WAY 0 starting at the top */ @@ -192,7 +192,7 @@ done_cache_as_ram_main: mov string, %ebx ; \ CALLSP(crt_console_tx_string) -# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) +# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) # else # define CONSOLE_DEBUG_TX_STRING(string) @@ -333,26 +333,26 @@ crt_console_tx_string: RETSP 9: /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif /* Data */ -#define TTYS0_RBR (TTYS0_BASE+0x00) +#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) /* Control */ #define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (TTYS0_BASE+0x01) -#define TTYS0_IIR (TTYS0_BASE+0x02) +#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) +#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) #define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (TTYS0_BASE+0x03) -#define TTYS0_MCR (TTYS0_BASE+0x04) +#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) +#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) #define TTYS0_DLL TTYS0_RBR #define TTYS0_DLM TTYS0_IER /* Status */ -#define TTYS0_LSR (TTYS0_BASE+0x05) -#define TTYS0_MSR (TTYS0_BASE+0x06) -#define TTYS0_SCR (TTYS0_BASE+0x07) +#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) +#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) +#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) mov %al, %ah 10: mov $TTYS0_LSR, %dx diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c index 4df30f4b8a..53cd4aa9c9 100644 --- a/src/cpu/amd/model_lx/syspreinit.c +++ b/src/cpu/amd/model_lx/syspreinit.c @@ -39,7 +39,7 @@ void SystemPreInit(void) { /* they want a jump ... */ -#ifndef USE_DCACHE_RAM +#ifndef CONFIG_USE_DCACHE_RAM __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); #endif StartTimer1(); diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c index 9c47a4f6d9..0a749da90a 100644 --- a/src/cpu/amd/model_lx/vsmsetup.c +++ b/src/cpu/amd/model_lx/vsmsetup.c @@ -292,7 +292,7 @@ void do_vsmbios(void) */ //VSA is cat onto the end after LB builds - rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024); + rom = ((unsigned long)0) - (CONFIG_ROM_SIZE + 36 * 1024); buf = (unsigned char *)VSA2_BUFFER; olen = unrv2b((uint8_t *) rom, buf, &ilen); printk_debug("buf ilen %d olen%d\n", ilen, olen); diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c index 948d4ac83b..c633c957f0 100644 --- a/src/cpu/amd/mtrr/amd_earlymtrr.c +++ b/src/cpu/amd/mtrr/amd_earlymtrr.c @@ -41,11 +41,11 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs) msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK); wrmsr(TOP_MEM, msr); -#if defined(XIP_ROM_SIZE) +#if defined(CONFIG_XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. */ - set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index e8e9273868..3d72fe684e 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -180,7 +180,7 @@ void amd_setup_mtrrs(void) /* FIXME we should probably query the cpu for this * but so far this is all any recent AMD cpu has supported. */ - address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 + address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index 4d4e11648f..999c51807c 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num) if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); + printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); enable_apic_ext_id(sysconf.nodes); } diff --git a/src/cpu/amd/socket_AM2/Config.lb b/src/cpu/amd/socket_AM2/Config.lb index de3c04608f..095643bd91 100644 --- a/src/cpu/amd/socket_AM2/Config.lb +++ b/src/cpu/amd/socket_AM2/Config.lb @@ -1,15 +1,15 @@ -uses K8_REV_F_SUPPORT -uses K8_HT_FREQ_1G_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE +uses CONFIG_K8_REV_F_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE config chip.h -default K8_REV_F_SUPPORT=1 +default CONFIG_K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 -default DIMM_SUPPORT=0x0004 #DDR2 unbuffered -default CPU_SOCKET_TYPE=0x11 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_DIMM_SUPPORT=0x0004 #DDR2 unbuffered +default CONFIG_CPU_SOCKET_TYPE=0x11 object socket_AM2.o diff --git a/src/cpu/amd/socket_F/Config.lb b/src/cpu/amd/socket_F/Config.lb index 42afda14b8..72f2a1b4cb 100644 --- a/src/cpu/amd/socket_F/Config.lb +++ b/src/cpu/amd/socket_F/Config.lb @@ -1,15 +1,15 @@ -uses K8_REV_F_SUPPORT -uses K8_HT_FREQ_1G_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE +uses CONFIG_K8_REV_F_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE config chip.h -default K8_REV_F_SUPPORT=1 +default CONFIG_K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 -default DIMM_SUPPORT=0x0104 #DDR2 and REG -default CPU_SOCKET_TYPE=0x10 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG +default CONFIG_CPU_SOCKET_TYPE=0x10 object socket_F.o diff --git a/src/cpu/amd/socket_F_1207/Config.lb b/src/cpu/amd/socket_F_1207/Config.lb index 5777e356d4..5c0147af7e 100644 --- a/src/cpu/amd/socket_F_1207/Config.lb +++ b/src/cpu/amd/socket_F_1207/Config.lb @@ -17,37 +17,37 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses PCI_IO_CFG_EXT -uses MMCONF_SUPPORT -uses HT3_SUPPORT -uses EXT_RT_TBL_SUPPORT -uses EXT_CONF_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE -uses CBB -uses CDB -uses PCI_BUS_SEGN_BITS -uses CAR_FAM10 +uses CONFIG_PCI_IO_CFG_EXT +uses CONFIG_MMCONF_SUPPORT +uses CONFIG_HT3_SUPPORT +uses CONFIG_EXT_RT_TBL_SUPPORT +uses CONFIG_EXT_CONF_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE +uses CONFIG_CBB +uses CONFIG_CDB +uses CONFIG_PCI_BUS_SEGN_BITS +uses CONFIG_CAR_FAM10 config chip.h -default PCI_IO_CFG_EXT=1 +default CONFIG_PCI_IO_CFG_EXT=1 -default HT3_SUPPORT=1 -default EXT_RT_TBL_SUPPORT=0 -default EXT_CONF_SUPPORT=0 -default DIMM_SUPPORT=0x0104 #DDR2 and REG -default CPU_SOCKET_TYPE=0x10 +default CONFIG_HT3_SUPPORT=1 +default CONFIG_EXT_RT_TBL_SUPPORT=0 +default CONFIG_EXT_CONF_SUPPORT=0 +default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG +default CONFIG_CPU_SOCKET_TYPE=0x10 -default CAR_FAM10=1 +default CONFIG_CAR_FAM10=1 -if EXT_RT_TBL_SUPPORT - default CBB=0xff - default CDB=0 +if CONFIG_EXT_RT_TBL_SUPPORT + default CONFIG_CBB=0xff + default CONFIG_CDB=0 end -#default MMCONF_SUPPORT=1 -#default MMCONF_SUPPORT_DEFAULT=1 +#default CONFIG_MMCONF_SUPPORT=1 +#default CONFIG_MMCONF_SUPPORT_DEFAULT=1 object socket_F_1207.o diff --git a/src/cpu/amd/socket_S1G1/Config.lb b/src/cpu/amd/socket_S1G1/Config.lb index 5cdc3bffab..6aa6b5a45b 100644 --- a/src/cpu/amd/socket_S1G1/Config.lb +++ b/src/cpu/amd/socket_S1G1/Config.lb @@ -1,15 +1,15 @@ -uses K8_REV_F_SUPPORT -uses K8_HT_FREQ_1G_SUPPORT -uses DIMM_SUPPORT -uses CPU_SOCKET_TYPE +uses CONFIG_K8_REV_F_SUPPORT +uses CONFIG_K8_HT_FREQ_1G_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE config chip.h -default K8_REV_F_SUPPORT=1 +default CONFIG_K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 -default DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1 -default CPU_SOCKET_TYPE=0x12 +default CONFIG_K8_HT_FREQ_1G_SUPPORT=1 +default CONFIG_DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1 +default CONFIG_CPU_SOCKET_TYPE=0x12 object socket_S1G1.o |