diff options
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/init_cpus.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/pi/s3_resume.c | 4 |
6 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 5f486f2fea..3a60b8d06c 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -75,11 +75,11 @@ static void set_resume_cache(void) msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); wrmsr(SYSCFG_MSR, msr); - /* Enable caching for 0 - coreboot ram using variable mtrr */ + /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ msr.lo = 0 | MTRR_TYPE_WRBACK; msr.hi = 0; wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; + msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; wrmsr(MTRR_PHYS_MASK(0), msr); diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 0a59696b56..1880ccb441 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -175,8 +175,8 @@ void cache_as_ram_new_stack (void) disable_cache_as_ram_bsp(); disable_cache(); - /* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */ - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); + /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ + set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); if (acpi_is_wakeup_s3()) { diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index c1ff24042d..0edded2b8c 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -519,7 +519,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) /* AP is ready, configure MTRRs and go to sleep */ if (set_mtrrs) - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); + set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); printk(BIOS_DEBUG, "Disabling CAR on AP %02x\n", apicid); if (is_fam15h()) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 8968e7e0be..51e1b7c849 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -326,7 +326,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) apicid); } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); + set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); #if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index b1e599acb1..cf0b08a04c 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -173,12 +173,12 @@ static void set_init_ecc_mtrrs(void) wrmsr(MTRR_PHYS_MASK(i), zero); } - /* Write back cache the first 1MB */ + /* Write back cache from 0x0 to CACHE_TMP_RAMTOP. */ msr.hi = 0x00000000; msr.lo = 0x00000000 | MTRR_TYPE_WRBACK; wrmsr(MTRR_PHYS_BASE(0), msr); msr.hi = 0x000000ff; - msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800; + msr.lo = ~((CACHE_TMP_RAMTOP) - 1) | 0x800; wrmsr(MTRR_PHYS_MASK(0), msr); /* Set the default type to write combining */ diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 53172d48f6..b6d363377a 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -271,11 +271,11 @@ static void set_resume_cache(void) msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); wrmsr(SYSCFG_MSR, msr); - /* Enable caching for 0 - coreboot ram using variable mtrr */ + /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ msr.lo = 0 | MTRR_TYPE_WRBACK; msr.hi = 0; wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; + msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; wrmsr(MTRR_PHYS_MASK(0), msr); |