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-rw-r--r--src/cpu/amd/agesa/cache_as_ram.inc2
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c2
-rw-r--r--src/cpu/amd/geode_gx2/cache_as_ram.inc2
-rw-r--r--src/cpu/amd/geode_lx/cache_as_ram.inc2
-rw-r--r--src/cpu/amd/pi/cache_as_ram.inc2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 80344cea2a..293e9a5077 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -80,7 +80,7 @@ cache_as_ram_setup:
movl $0xc00000e3, 0x18(%edi)
movl %eax, 0x1c(%edi)
- # load rom based identity mapped page tables
+ # load ROM based identity mapped page tables
mov %ecx, %eax
mov %eax, %cr3
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index ad5a5c7dcf..19aa0a2fe6 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -166,7 +166,7 @@ void post_cache_as_ram(void)
void cache_as_ram_new_stack (void)
{
- print_car_debug("Disabling cache as ram now\n");
+ print_car_debug("Disabling cache as RAM now\n");
disable_cache_as_ram_bsp();
disable_cache();
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index bd9de282a8..c31b95d91c 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -171,7 +171,7 @@ done_cache_as_ram_main:
pop %esi
pop %edi
- /* Clear the cache out to ram */
+ /* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index cbc5cb817d..d48f0e836c 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -198,7 +198,7 @@ done_cache_as_ram_main:
pop %esi
pop %edi
- /* Clear the cache out to ram */
+ /* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index fd5e66dc9c..40ec1b2fc2 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -81,7 +81,7 @@ cache_as_ram_setup:
movl $0xc00000e3, 0x18(%edi)
movl %eax, 0x1c(%edi)
- # load rom based identity mapped page tables
+ # load ROM based identity mapped page tables
mov %ecx, %eax
mov %eax, %cr3